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Amorphous carbon multilayer coating with directional protection |
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Halogen abatement for high aspect ratio channel device damage layer removal for EPI growth |
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Method for forming features in a silicon containing layer |
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Simplified litho-etch-litho-etch process |
Hun Sang Kim, Shinichi Koseki |
2016-08-23 |
| 9281190 |
Local and global reduction of critical dimension (CD) asymmetry in etch processing |
Kang-Lie Chiang, Olivier Luere |
2016-03-08 |
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Aspect ratio dependent etch (ARDE) lag reduction process by selective oxidation with inert gas sputtering |
Jinsu Kim, Xiaosong Ji, Ho Jeong Kim, Byungkook Kong, Hoon Sang Lee |
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Multi-film stack etching with polymer passivation of an overlying etched layer |
Sunil Srinivasan, Anisul Khan |
2014-06-10 |
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Reducing gate CD bias in CMOS processing |
Freidoon Mehrad, Frank Scott Johnson |
2011-03-22 |
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Post metal gate VT adjust etch clean |
Brian K. Kirkpatrick, Randall W. Pak |
2010-08-31 |
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Process for etching tungsten silicide overlying polysilicon particularly in a flash memory |
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2010-06-08 |
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Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode |
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2008-05-06 |
| 6756313 |
Method of etching silicon nitride spacers with high selectivity relative to oxide in a high density plasma chamber |
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