Issued Patents All Time
Showing 176–200 of 229 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7285818 | Non-volatile two-transistor programmable logic cell and array layout | Fethi Dhaoui, John McCollum, Vidyadhara Bellippady | 2007-10-23 |
| 7283398 | Method for minimizing false detection of states in flash memory devices | Yue-Song He, Richard Fastow, Takao Akaogi, Wing Leung | 2007-10-16 |
| 7272060 | Method, system, and circuit for performing a memory related operation | Qiang Lu, Richard Fastow | 2007-09-18 |
| 7210082 | Method for performing ATPG and fault simulation in a scan-based integrated circuit | Khader S. Abdel-Hafez, Laung-Terng Wang, Boryau (Jack) Sheu, Zhigang Jiang | 2007-04-24 |
| 7170130 | Memory cell with reduced DIBL and Vss resistance | Shenqing Fang, Kuo-Tung Chang, Pavel Fastenko | 2007-01-30 |
| 7151028 | Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability | Shenqing Fang, Rinji Sugino, Kuo-Tung Chang, Kazuhiro Mizutani, Pavel Fastenko | 2006-12-19 |
| 7042767 | Flash memory unit and method of programming a flash memory device | Nian Yang, Zhizheng Liu | 2006-05-09 |
| 7042766 | Method of programming a flash memory device using multilevel charge storage | Nian Yang, Zhizheng Liu | 2006-05-09 |
| 7020022 | Method of reference cell design for optimized memory circuit yield | John Jianshi Wang, Xin Guo | 2006-03-28 |
| 6991987 | Method for producing a low defect homogeneous oxynitride | Xin Guo, Nian Yang | 2006-01-31 |
| 6987696 | Method of improving erase voltage distribution for a flash memory array having dummy wordlines | Nian Yang, Shenqing Fang | 2006-01-17 |
| 6963506 | Circuit and technique for accurately sensing low voltage flash memory devices | Nian Yang, Yue-Song He | 2005-11-08 |
| 6898124 | Efficient and accurate sensing circuit and technique for low voltage flash memory devices | Nian Yang, Yue-Song He | 2005-05-24 |
| 6894925 | Flash memory cell programming method and system | Sheunghee Park, Sameer Haddad, Chi Chang, Richard Fastow, Ming Sang Kwan | 2005-05-17 |
| 6888157 | N-Gate/N-Substrate or P-Gate/P-Substrate capacitor to characterize polysilicon gate depletion evaluation | Nian Yang, Yue-Song He | 2005-05-03 |
| 6884638 | METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED | Tien-Chun Yang, Nian Yang | 2005-04-26 |
| 6864106 | Method and system for detecting tunnel oxide encroachment on a memory device | Nian Yang, Xin Guo | 2005-03-08 |
| 6859748 | Test structure for measuring effect of trench isolation on oxide in a memory device | Nian Yang, Tien-Chun Yang | 2005-02-22 |
| 6852594 | Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18μm flash memory technology | Yue-Song He, Richard Fastow | 2005-02-08 |
| 6828623 | Floating gate memory device with homogeneous oxynitride tunneling dielectric | Xin Guo, Nian Yang | 2004-12-07 |
| 6825526 | Structure for increasing drive current in a memory array and related method | Yue-Song He, Nian Yang | 2004-11-30 |
| 6822259 | Method of detecting and distinguishing stack gate edge defects at the source or drain junction | Nian Yang, Xin Guo | 2004-11-23 |
| 6818462 | METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED | Tien-Chun Yang, Nian Yang | 2004-11-16 |
| 6812514 | High density floating gate flash memory and fabrication processes therefor | Nian Yang, Hyeon-Seag Kim | 2004-11-02 |
| 6808945 | Method and system for testing tunnel oxide on a memory-related structure | Hsiao-Han Thio, Nian Yang | 2004-10-26 |