Issued Patents All Time
Showing 201–225 of 229 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6797650 | Flash memory devices with oxynitride dielectric as the charge storage media | Nian Yang, John Jianshi Wang, Jiang Li | 2004-09-28 |
| 6777957 | Test structure to measure interlayer dielectric effects and breakdown and detect metal defects in flash memories | Nian Yang, John Jianshi Wang | 2004-08-17 |
| 6759295 | METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED | Tien-Chun Yang, Nian Yang | 2004-07-06 |
| 6756806 | Method of determining location of gate oxide breakdown of MOSFET by measuring currents | Nian Yang, Tien-Chun Yang | 2004-06-29 |
| 6754109 | Method of programming memory cells | Richard Fastow, Sameer Haddad, Sheung-Hee Park | 2004-06-22 |
| 6751146 | System and method for charge restoration in a non-volatile memory device | Jianshi Wang, Imran Khan | 2004-06-15 |
| 6731130 | Method of determining gate oxide thickness of an operational MOSFET | Nian Yang, Tien-Chun Yang | 2004-05-04 |
| 6716710 | Using a first liner layer as a spacer in a semiconductor device | Hsiao-Han Thio, Nian Yang | 2004-04-06 |
| 6717850 | Efficient method to detect process induced defects in the gate stack of flash memory devices | Jiang Li, Nian Yang, John Jianshi Wang | 2004-04-06 |
| 6696331 | Method of protecting a stacked gate structure during fabrication | Nian Yang, Hsiao-Han Thio | 2004-02-24 |
| 6689666 | Replacing a first liner layer with a thicker oxide layer when forming a semiconductor device | Hsiao-Han Thio, Nian Yang | 2004-02-10 |
| 6677442 | Nucleic acid encoding human REV1 protein | Wensheng Lin, Hua Xin, Xiaohua Wu | 2004-01-13 |
| 6660588 | High density floating gate flash memory and fabrication processes therefor | Nian Yang, Hyeon-Seag Kim | 2003-12-09 |
| 6646462 | Extraction of drain junction overlap with the gate and the channel length for ultra-small CMOS devices with ultra-thin gate oxides | Nian Yang, Xin Guo | 2003-11-11 |
| 6642106 | Method for increasing core gain in flash memory device using strained silicon | Nian Yang, Hyeon-Seag Kim | 2003-11-04 |
| 6643185 | Method for repairing over-erasure of fast bits on floating gate memory devices | Nian Yang, Jiang Li | 2003-11-04 |
| 6617639 | Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling | Xin Guo, Yue-Song He | 2003-09-09 |
| 6606273 | Methods and systems for flash memory tunnel oxide reliability testing | Xin Guo, Nian Yang | 2003-08-12 |
| 6596586 | Method of forming low resistance common source line for flash memory devices | Nian Yang, Un Soon Kim | 2003-07-22 |
| 6593590 | Test structure apparatus for measuring standby current in flash memory devices | Nian Yang, Tien-Chun Yang | 2003-07-15 |
| 6590260 | Memory device having improved programmability | Nian Yang, John Jianshi Wang | 2003-07-08 |
| 6576487 | Method to distinguish an STI outer edge current component with an STI normal current component | Harpreet Sachar, Kuo-Tung Chang | 2003-06-10 |
| 6570787 | Programming with floating source for low power, low leakage and high density flash memory devices | Nian Yang, Xin Guo | 2003-05-27 |
| 6541338 | Low defect density process for deep sub-0.18 &mgr;m flash memory technologies | Yue-Song He, Richard Fastow | 2003-04-01 |
| 6510085 | Method of channel hot electron programming for short channel NOR flash arrays | Richard Fastow, Sheunghee Park, Sameer Haddad, Chi Chang | 2003-01-21 |