BS

Boryau (Jack) Sheu

ST Syntest Technologies: 11 patents #9 of 31Top 30%
📍 San Jose, CA: #5,837 of 32,062 inventorsTop 20%
🗺 California: #55,401 of 386,348 inventorsTop 15%
Overall (All Time): #467,632 of 4,157,543Top 15%
11
Patents All Time

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDate
7945833 Method and apparatus for pipelined scan compression Laung-Terng Wang, Nur A. Touba, Shianling Wu, Zhigang Jiang 2011-05-17
7779322 Compacting test responses using X-driven compactor Zhigang Wang, Laung-Terng Wang, Shianling Wu, Xiaoqing Wen, Zhigang Jiang 2010-08-17
7735049 Mask network design for scan-based integrated circuits Laung-Terng Wang, Xiaoqing Wen 2010-06-08
7721172 Method and apparatus for broadcasting test patterns in a scan-based integrated circuit Laung-Terng Wang, Zhigang Jiang, Zhigang Wang, Shianling Wu 2010-05-18
7590905 Method and apparatus for pipelined scan compression Khader S. Abdel-Hafez, Laung-Terng Wang, Shianling Wu 2009-09-15
7512851 Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Fei-Sheng Hsu, Augusli Kifli +4 more 2009-03-31
7412637 Method and apparatus for broadcasting test patterns in a scan based integrated circuit Laung-Terng Wang, Zhigang Jiang, Zhigang Wang, Shianling Wu 2008-08-12
7231570 Method and apparatus for multi-level scan compression Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu 2007-06-12
7210082 Method for performing ATPG and fault simulation in a scan-based integrated circuit Khader S. Abdel-Hafez, Laung-Terng Wang, Zhigang Wang, Zhigang Jiang 2007-04-24
7124342 Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Shun-Miin (Sam) Wang 2006-10-17
7032148 Mask network design for scan-based integrated circuits Laung-Terng Wang, Shun-Miin (Sam) Wang, Khader S. Abdel-Hafez, Xiaoqing Wen 2006-04-18