XW

Xiaoqing Wen

ST Syntest Technologies: 32 patents #2 of 31Top 7%
KT Kyushu Institute Of Technology: 7 patents #6 of 237Top 3%
JA Japan Science And Technology Agency: 4 patents #144 of 2,171Top 7%
SC System Jd Co.: 4 patents #5 of 9Top 60%
TE Tencent: 1 patents #4,257 of 8,131Top 55%
📍 Lo Wu, CA: #119 of 469 inventorsTop 30%
Overall (All Time): #66,965 of 4,157,543Top 2%
44
Patents All Time

Issued Patents All Time

Showing 1–25 of 44 patents

Patent #TitleCo-InventorsDate
12318692 Virtual object control method and apparatus, terminal, and storage medium Jiaqi Pan, Ying Deng, Ke Mao, Weixiang YU, Jing Kou +1 more 2025-06-03
9696377 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit Laung-Terng Wang, Hsin-Po Wang, Meng-Chyi Lin, Shyh-Horng Lin, Ta-Chia Yeh +2 more 2017-07-04
9678156 Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test Laung-Terng Wang, Po-Ching Hsu 2017-06-13
9316688 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test Laung-Terng Wang, Po-Ching Hsu 2016-04-19
9274168 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test Laung-Terng Wang, Po-Ching Hsu 2016-03-01
9091730 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test Laung-Terng Wang, Po-Ching Hsu 2015-07-28
8775985 Computer-aided design system to automate scan synthesis at register-transfer level Laung-Terng Wang 2014-07-08
8589751 Don't-care-bit identification method and don't-care-bit identification program Kohei Miyase, Seiji Kajihara 2013-11-19
8543950 Computer-aided design system to automate scan synthesis at register-transfer level Laung-Terng Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Shyh-Horng Lin +1 more 2013-09-24
8453023 Target logic value determination method for unspecified bit in test vector for combinational circuit and non-transitory computer-readable medium Kohei Miyase, Seiji Kajihara 2013-05-28
8429472 Generating device, generating method, and program Kohei Miyase, Seiji Kajihara, Yuta YAMATO 2013-04-23
8219945 Computer-aided design system to automate scan synthesis at register-transfer level Laung-Terng Wang 2012-07-10
8117513 Test method and test program of semiconductor logic circuit device Seiji Kajihara 2012-02-14
8001437 Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit Kohei Miyase, Seiji Kajihara 2011-08-16
7979765 Generating device, generating method, program and recording medium Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Hiroshi Date 2011-07-12
7971118 Conversion device, conversion method, program, and recording medium Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Hiroshi Date 2011-06-28
7962822 Generating device, generating method, program and recording medium Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Hiroshi Date 2011-06-14
7945830 Method and apparatus for unifying self-test with scan-test during prototype debug and production test Laung-Terng Wang 2011-05-17
7913144 Diagnostic device, diagnostic method, program, and recording medium Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Hiroshi Date 2011-03-22
7904857 Computer-aided design system to automate scan synthesis at register-transfer level Laung-Terng Wang 2011-03-08
7904773 Multiple-capture DFT system for scan-based integrated circuits Laung-Terng Wang, Meng-Chyi Lin, Hsin-Po Wang, Chi-Chan Hsu, Shih-Chia Kao +1 more 2011-03-08
7779322 Compacting test responses using X-driven compactor Zhigang Wang, Laung-Terng Wang, Shianling Wu, Boryau (Jack) Sheu, Zhigang Jiang 2010-08-17
7779323 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang +1 more 2010-08-17
7747920 Method and apparatus for unifying self-test with scan-test during prototype debug and production test Laung-Terng Wang 2010-06-29
7743306 Test vector generating method and test vector generating program of semiconductor logic circuit device Seiji Kajihara 2010-06-22