Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6430639 | Minimizing use of bus command code points to request the start and end of a lock | William Kurt Lewchuk | 2002-08-06 |
| 6427193 | Deadlock avoidance using exponential backoff | William A. Hughes | 2002-07-30 |
| 6424688 | Method to transfer data in a system with multiple clock domains using clock skipping techniques | Teik-Chung Tan, Brian D. McMinn | 2002-07-23 |
| 6405304 | Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | James Arthur Farrell, Sharon Marie Britton, Harry Ray Fair, III, Bruce Gieseke, Daniel Leibholz | 2002-06-11 |
| 6405305 | Rapid execution of floating point load control word instructions | Stephan G. Meier, Jeffrey E. Trull, Norbert Juffa | 2002-06-11 |
| 6393502 | System and method for initiating a serial data transfer between two clock domains | Philip E. Madrid | 2002-05-21 |
| 6374344 | Methods and apparatus for processing load instructions in the presence of RAM array and data bus conflicts | David A. Webb, James B. Keller | 2002-04-16 |
| 6360314 | Data cache having store queue bypass for out-of-order instruction execution and method for same | David A. Webb, James B. Keller | 2002-03-19 |
| 6275905 | Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system | James B. Keller | 2001-08-14 |
| 6266744 | Store to load forwarding using a dependency link file | William A. Hughes | 2001-07-24 |
| 6253301 | Method and apparatus for a dedicated physically indexed copy of the data cache tag arrays | Rahul Razdan, David A. Webb, James B. Keller | 2001-06-26 |
| 6253304 | Collation of interrupt control devices | Larry D. Hewitt, David N. Suggs, Greg Smaus | 2001-06-26 |
| 6205541 | System and method using selection logic units to define stack orders | Thang M. Tran | 2001-03-20 |
| 6141734 | Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol | Rahul Razdan, David A. Webb, James B. Keller, Daniel Leibholz | 2000-10-31 |
| 6112296 | Floating point stack manipulation using a register map and speculative top of stack values | David B. Witt | 2000-08-29 |
| 6112018 | Apparatus for exchanging two stack registers | Thang M. Tran | 2000-08-29 |
| 6098166 | Speculative issue of instructions under a load miss shadow | Daniel Leibholz, Sven Meier, James Arthur Farrell, Timothy C. Fischer | 2000-08-01 |
| 6018798 | Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle | David B. Witt | 2000-01-25 |
| 5924120 | Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times | Rahul Razdan, David A. Webb, James B. Keller | 1999-07-13 |
| 5155843 | Error transition mode for multi-processor system | Rebecca L. Stamm, R. Iris Bahar, Michael A. Callander, Linda Chao, Douglas E. Sanders +3 more | 1992-10-13 |