Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8589629 | Method for way allocation and way locking in a cache | Jonathan Owen, Guhan Krishnan, Carl Dietz, Douglas R. Beard, Alexander J. Branover | 2013-11-19 |
| 6473832 | Load/store unit having pre-cache and post-cache queues for low latency load memory operations | Hebbalalu S. Ramagopal, William A. Hughes | 2002-10-29 |
| 6446189 | Computer system including a novel address translation mechanism | Gerald D. Zuraski, Jr., Frederick Daniel Weber, William A. Hughes, Scott White, Michael T. Clark | 2002-09-03 |
| 6430639 | Minimizing use of bus command code points to request the start and end of a lock | Derrick R. Meyer | 2002-08-06 |
| 6415360 | Minimizing self-modifying code checks for uncacheable memory types | William A. Hughes, Gerald D. Zuraski, Jr. | 2002-07-02 |
| 5771247 | Low latency error reporting for high performance bus | Michael S. Allen, Ravi Kumar Arimilli, John Michael Kaiser | 1998-06-23 |
| 5745698 | System and method for communicating between devices | Michael S. Allen, Ravi Kumar Arimilli, John Michael Kaiser | 1998-04-28 |
| 5687327 | System and method for allocating bus resources in a data processing system | Ravi Kumar Arimilli, John Michael Kaiser, Michael S. Allen | 1997-11-11 |
| 5671370 | Alternating data valid control signals for high performance data transfer | Michael S. Allen, Ravi Kumar Arimilli, John Michael Kaiser | 1997-09-23 |
| 5659708 | Cache coherency in a multiprocessing system | Ravi Kumar Arimilli, John Michael Kaiser, Michael S. Allen | 1997-08-19 |
| 5608878 | Dual latency status and coherency reporting for a multiprocessing system | Ravi Kumar Arimilli, John Michael Kaiser, Michael S. Allen | 1997-03-04 |