Issued Patents All Time
Showing 26–50 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6645679 | Attenuated phase shift mask for use in EUV lithography and a method of making such a mask | Bruno La Fontaine, Harry J. Levinson, Kouros Ghandehari | 2003-11-11 |
| 6632707 | Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning | Fei Wang, Lynne A. Okada, Ramkumar Subramanian, James Kai, Lu You | 2003-10-14 |
| 6627536 | Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides | — | 2003-09-30 |
| 6610608 | Plasma etching using combination of CHF3 and CH3F | Lynne A. Okada, Fei Wang | 2003-08-26 |
| 6603206 | Slot via filled dual damascene interconnect structure without middle etch stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2003-08-05 |
| 6599839 | Plasma etch process for nonhomogenous film | Lynne A. Okada, Dawn Hopper, Suzette K. Pangrle, Fei Wang | 2003-07-29 |
| 6593037 | EUV mask or reticle having reduced reflections | Bruno M. LaFontaine, Harry J. Levinson | 2003-07-15 |
| 6583046 | Post-treatment of low-k dielectric for prevention of photoresist poisoning | Lynne A. Okada, Fei Wang | 2003-06-24 |
| 6569757 | Methods for forming co-axial interconnect lines in a CMOS process for high speed applications | Milind Weling, Subhas Bothra, Michael N. Misheloff | 2003-05-27 |
| 6545338 | Methods for implementing co-axial interconnect lines in a CMOS process for high speed RF and microwave applications | Subhas Bothra, Michael N. Misheloff, Milind Weling | 2003-04-08 |
| 6541359 | Optimized gate implants for reducing dopant effects during gate etching | Tammy Zheng, Emmanuel de Muizon, Linda Leard | 2003-04-01 |
| 6534397 | Pre-treatment of low-k dielectric for prevention of photoresist poisoning | Lynne A. Okada, Fei Wang | 2003-03-18 |
| 6521524 | Via filled dual damascene structure with middle stop layer and method for making the same | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2003-02-18 |
| 6518646 | Semiconductor device with variable composition low-k inter-layer dielectric and method of making | Dawn Hopper, Suzette K. Pangrle, Richard J. Huang, Lu You | 2003-02-11 |
| 6495447 | Use of hydrogen doping for protection of low-k dielectric layers | Lynne A. Okada | 2002-12-17 |
| 6475929 | Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant | Suzette K. Pangrle, Lynne A. Okada, Fei Wang | 2002-11-05 |
| 6472231 | Dielectric layer with treated top surface forming an etch stop layer and method of making the same | Lynne A. Okada | 2002-10-29 |
| 6465340 | Via filled dual damascene structure with middle stop layer and method for making the same | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-10-15 |
| 6465889 | Silicon carbide barc in dual damascene processing | Ramkumar Subramanian, Fei Wang, Lynne A. Okada, Darrell M. Erb | 2002-10-15 |
| 6451673 | Carrier gas modification for preservation of mask layer during plasma etching | Lynne A. Okada | 2002-09-17 |
| 6448654 | Ultra thin etch stop layer for damascene process | Lynne A. Okada | 2002-09-10 |
| 6444573 | Method of making a slot via filled dual damascene structure with a middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-09-03 |
| 6429116 | Method of fabricating a slot dual damascene structure without middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-08-06 |
| 6410210 | Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides | — | 2002-06-25 |
| 6391766 | Method of making a slot via filled dual damascene structure with middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-05-21 |