Issued Patents All Time
Showing 51–75 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6387720 | Waveguide structures integrated with standard CMOS circuitry and methods for making the same | Michael N. Misheloff, Subhas Bothra, Milind Weling | 2002-05-14 |
| 6383919 | Method of making a dual damascene structure without middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-05-07 |
| 6380092 | Gas phase planarization process for semiconductor wafers | Rao Annapragada, Milind Weling | 2002-04-30 |
| 6372631 | Method of making a via filled dual damascene structure without middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-04-16 |
| 6372635 | Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-04-16 |
| 6365505 | Method of making a slot via filled dual damascene structure with middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-04-02 |
| 6361706 | Method for reducing the amount of perfluorocompound gas contained in exhaust emissions from plasma processing | — | 2002-03-26 |
| 6342428 | Method for a consistent shallow trench etch profile | Tammy Zheng, Edward Yeh | 2002-01-29 |
| 6323113 | Intelligent gate-level fill methods for reducing global pattern density effects | Tammy Zheng, Subhas Bothra, Harlan Lee Sur, Jr. | 2001-11-27 |
| 6316834 | Tungsten plugs for integrated circuits and method for making same | Dipankar Pramanik, Xi-Wei Lin | 2001-11-13 |
| 6297170 | Sacrificial multilayer anti-reflective coating for mos gate formation | Jacob D. Haskell, Satyendra Sethi | 2001-10-02 |
| 6267076 | Gas phase planarization process for semiconductor wafers | Rao Annapragada, Milind Weling | 2001-07-31 |
| 6255226 | Optimized metal etch process to enable the use of aluminum plugs | Tammy Zheng, Samit Sengupta | 2001-07-03 |
| 6229685 | Thin capacitive structures and methods for making the same | Subhas Bothra, Dipankar Pramanik | 2001-05-08 |
| 6211087 | Chemical wet etch removal of underlayer material after performing chemical mechanical polishing on a primary layer | Milind Weling | 2001-04-03 |
| 6207565 | Integrated process for ashing resist and treating silicon after masked spacer etch | Edward Yeh, Samit Sengupta | 2001-03-27 |
| 6107158 | Method of manufacturing a trench structure in a semiconductor substrate | Jie Zheng, Suzanne Monsees | 2000-08-22 |
| 6103457 | Method for reducing faceting on a photoresist layer during an etch process | — | 2000-08-15 |
| 6080677 | Method for preventing micromasking in shallow trench isolation process etching | Ian Robert Harvey, Linda Leard | 2000-06-27 |
| 6060376 | Integrated etch process for polysilicon/metal gate | Xi-Wei Lin, Tammy Zheng, Linda Leard, Ian Robert Harvey | 2000-05-09 |
| 6057245 | Gas phase planarization process for semiconductor wafers | Rao Annapragada, Milind Weling | 2000-05-02 |
| 6027950 | Method for achieving accurate SOG etchback selectivity | Ian Robert Harvey | 2000-02-22 |
| 6022265 | Complementary material conditioning system for a chemical mechanical polishing machine | Charles Franklin Drill, Milind Weling, Richard Russ, David E. Henderson | 2000-02-08 |
| 6013558 | Silicon-enriched shallow trench oxide for reduced recess during LDD spacer etch | Ian Robert Harvey, Milind Weling | 2000-01-11 |
| 5990561 | Tungsten plugs for integrated circuits and methods for making same | Dipankar Pramanik, Xi-Wei Lin | 1999-11-23 |