CG

Calvin T. Gabriel

AM AMD: 40 patents #206 of 9,279Top 3%
VT Vlsi Technology: 39 patents #3 of 594Top 1%
SL Spansion Llc.: 8 patents #114 of 769Top 15%
PA Philips Electronics North America: 7 patents #43 of 725Top 6%
Philips: 5 patents #1,000 of 7,731Top 15%
PS Philips Semiconductors: 2 patents #8 of 64Top 15%
Cypress Semiconductor: 2 patents #733 of 1,852Top 40%
VT Vlsip Technologies: 1 patents #1 of 9Top 15%
📍 Cupertino, CA: #82 of 6,989 inventorsTop 2%
🗺 California: #2,203 of 386,348 inventorsTop 1%
Overall (All Time): #14,286 of 4,157,543Top 1%
101
Patents All Time

Issued Patents All Time

Showing 76–100 of 101 patents

Patent #TitleCo-InventorsDate
5976987 In-situ corner rounding during oxide etch for improved plug fill Ian Robert Harvey, Subhas Bothra 1999-11-02
5965941 Use of dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing Milind Weling, Subhas Bothra 1999-10-12
5939765 Sidewall profile Jie Zheng, Suzanne Monsees 1999-08-17
5939791 Electrically conductive interconnects for integrated circuits Teresa Trowbridge 1999-08-17
5882982 Trench isolation method Jie Zheng, Suzanne Monsees 1999-03-16
5861342 Optimized structures for dummy fill mask design Milind Weling 1999-01-19
5821163 Method for achieving accurate SOG etchback selectivity Ian Robert Harvey 1998-10-13
5804502 Tungsten plugs for integrated circuits and methods for making same Dipankar Pramanik, Xi-Wei Lin 1998-09-08
5776821 Method for forming a reduced width gate electrode Jacob D. Haskell, Satyendra Sethi 1998-07-07
5753561 Method for making shallow trench isolation structure having rounded corners Henry Lee, Jie Zheng 1998-05-19
5730834 Fluorine residue removal after tungsten etchback 1998-03-24
5702978 Sloped silicon nitride etch for smoother field oxide edge Olivier Laparra 1997-12-30
5639697 Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing Milind Weling, Subhas Bothra 1997-06-17
5638006 Method and apparatus for wafer level prediction of thin oxide reliability using differentially sized gate-like antennae Subhash R. Nariani 1997-06-10
5548224 Method and apparatus for wafer level prediction of thin oxide reliability Subhash R. Nariani 1996-08-20
5522957 Method for leak detection in etching chambers Milind Weling, Vivek Jain, Dipankar Pramanik 1996-06-04
5462892 Semiconductor processing method for preventing corrosion of metal film connections 1995-10-31
5420796 Method of inspecting planarity of wafer surface after etchback step in integrated circuit fabrication Milind Weling 1995-05-30
5405488 System and method for plasma etching endpoint detection Dimitrios Dimitrelis, Samuel V. Dunton 1995-04-11
5397433 Method and apparatus for patterning a metal layer 1995-03-14
5328865 Method for making cusp-free anti-fuse structures William J. Boardman, David P. Chan, Kuang-Yeh Chang, Vivek Jain, Subhash R. Nariani 1994-07-12
5294295 Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges 1994-03-15
5290734 Method for making anti-fuse structures William J. Boardman, David P. Chan, Kuang-Yeh Chang, Vivek Jain, Subhash R. Nariani 1994-03-01
5198072 Method and apparatus for detecting imminent end-point when etching dielectric layers in a plasma etch system 1993-03-30
5120679 Anti-fuse structures and methods for making same William J. Boardman, David P. Chan, Kuang-Yeh Chang, Vivek Jain, Subhash R. Nariani 1992-06-09