Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
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Hung-Sheng Chen — 55 Patents

UMUnited Microelectronics: 10 patents #574 of 4,560Top 15%
ALAltek: 10 patents #12 of 158Top 8%
AMD: 9 patents #1,329 of 9,279Top 15%
NSNational Semiconductor: 7 patents #267 of 2,238Top 15%
WIWistron: 6 patents #164 of 2,107Top 8%
ATAplus Flash Technology: 6 patents #5 of 13Top 40%
ACActel: 3 patents #69 of 156Top 45%
Fujitsu Limited: 2 patents #10,930 of 24,456Top 45%
PEPrimax Electronics: 2 patents #210 of 571Top 40%
AEAdvanced Semiconductor Engineering: 2 patents #403 of 1,073Top 40%
FLFujitsu Amd Semiconductor Limited: 1 patents #14 of 40Top 35%
Taichung, CA: #21 of 193 inventorsTop 15%
Overall (All Time): #44,930 of 4,157,543Top 2%
55 Patents All Time

Issued Patents All Time

Showing 26–50 of 55 patents

Patent #TitleCo-InventorsDate
7924222 Method for obtaining precise intermediate frequency of global positioning system (GPS) 2011-04-12
7916076 Method for calculating current position coordinate 2011-03-29
7916077 Method for obtaining correct phase inversion points in signal of GPS 2011-03-29
7911377 Method for obtaining precise tracking frequency of GPS signal 2011-03-22
7884761 Method for tracking satellite signal by GPS 2011-02-08
7590000 Non-volatile programmable memory cell for programmable logic array John McCollum, Frank Hawley 2009-09-15
7245535 Non-volatile programmable memory cell for programmable logic array John McCollum, Frank Hawley 2007-07-17
6891221 Array architecture and process flow of nonvolatile memory devices for mass storage applications Peter Wung Lee, Vei-Han Chan 2005-05-10
6841846 Antifuse structure and a method of forming an antifuse structure Huan-Chung Tseng, Chang-Kai Huang 2005-01-11
6808988 Method for forming isolation in flash memory wafer Yowjuang W. Liu 2004-10-26
6717846 Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration Peter Wung Lee, Vei-Han Chan 2004-04-06
6660585 Stacked gate flash memory cell with reduced disturb conditions Peter Wung Lee, Hsing-Ya Tsao, Vei-Han Chan, Fu-Chang Hsu 2003-12-09
6444530 Process for fabricating an integrated circuit with a self-aligned contact Unsoon Kim, Yu Sun, Chi Chang, Mark T. Ramsbey, Mark Randolph +4 more 2002-09-03
6444539 Method for producing a shallow trench isolation filled with thermal oxide Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark S. Chang +1 more 2002-09-03
6262622 Breakdown-free high voltage input circuitry Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Vei-Han Chan 2001-07-17
6258668 Array architecture and process flow of nonvolatile memory devices for mass storage applications Peter Wung Lee, Vei-Han Chan 2001-07-10
6232646 Shallow trench isolation filled with thermal oxide Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark S. Chang +1 more 2001-05-15
6134150 Erase condition for flash memory Fu-Chang Hsu, Hsing-Ya Tsao, Peter Wung Lee, Vei-Han Chan 2000-10-17
6124640 Scalable and reliable integrated circuit inter-level dielectric Kashmir Sahota, Richard J. Huang, Yu Sun 2000-09-26
6103593 Method and system for providing a contact on a semiconductor device Angela T. Hui, Unsoon Kim 2000-08-15
6004862 Core array and periphery isolation technique Unsoon Kim, Kashmir Sahota, Yu Sun 1999-12-21
5945352 Method for fabrication of shallow isolation trenches with sloped wall profiles Mark S. Chang 1999-08-31
5943564 BiCMOS process for forming double-poly MOS and bipolar transistors with substantially identical device architectures Chih Sieh Teng 1999-08-24
5907781 Process for fabricating an integrated circuit with a self-aligned contact Unsoon Kim, Yu Sun, Chi Chang, Mark T. Ramsbey, Mark Randolph +4 more 1999-05-25
5899723 Oblique implantation in forming base of bipolar transistor Chih Sieh Teng 1999-05-04