Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7879669 | Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length | Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala | 2011-02-01 |
| 7145191 | P-channel field-effect transistor with reduced junction capacitance | Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala | 2006-12-05 |
| 6797576 | Fabrication of p-channel field-effect transistor for reducing junction capacitance | Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala | 2004-09-28 |
| 6146958 | Methods for making VLSI capacitors and high Q VLSI inductors using metal-filled via plugs | Ji-Cheng Zhao | 2000-11-14 |
| 5943564 | BiCMOS process for forming double-poly MOS and bipolar transistors with substantially identical device architectures | Hung-Sheng Chen | 1999-08-24 |
| 5908311 | Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells | Min-hwa Chi, Albert Bergemont | 1999-06-01 |
| 5899723 | Oblique implantation in forming base of bipolar transistor | Hung-Sheng Chen | 1999-05-04 |
| 5861647 | VLSI capacitors and high Q VLSI inductors using metal-filled via plugs | Ji-Cheng Zhao | 1999-01-19 |
| 5761126 | Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell | Min-hwa Chi, Albert Bergemont | 1998-06-02 |
| 5733813 | Method for forming planarized field isolation regions | Hung-Sheng Chen | 1998-03-31 |
| 5726069 | Use of oblique implantation in forming emitter of bipolar transistor | Hung-Sheng Chen | 1998-03-10 |
| 5607873 | Method for forming contact openings in a multi-layer structure that reduces overetching of the top conductive structure | Hung-Sheng Chen, Tim Nguyen, Larry Moberly | 1997-03-04 |
| 5605849 | Use of oblique implantation in forming base of bipolar transistor | Hung-Sheng Chen | 1997-02-25 |
| 5399513 | Salicide compatible CMOS process with a differential oxide implant mask | Tian-I Liou | 1995-03-21 |
| 4956311 | Double-diffused drain CMOS process using a counterdoping technique | Tian-I Liou | 1990-09-11 |
| 4877751 | Method of forming an N+ poly-to- N+ silicon capacitor structure utilizing a deep phosphorous implant | Tian-I Liou, Hiekyung Chun-Min | 1989-10-31 |