Issued Patents All Time
Showing 76–100 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8124453 | Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates | Ming Sun | 2012-02-28 |
| 8067822 | Integrated circuit package for semiconductor devices with improved electric resistance and inductance | Leeshawn Luo, Anup Bhalla, Sik Lui, Mike F. Chang | 2011-11-29 |
| 8058727 | Standing chip scale package | Tao Feng, Anup Bhalla | 2011-11-15 |
| 8053891 | Standing chip scale package | Tao Feng, Anup Bhalla | 2011-11-08 |
| 7955893 | Wafer level chip scale package and process of manufacture | Tao Feng, Francois Hebert, Ming Sun | 2011-06-07 |
| 7838977 | Packages for electronic devices implemented with laminated board with a top and a bottom patterned metal layers | Ming Sun | 2010-11-23 |
| 7829989 | Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside | Ming Sun | 2010-11-09 |
| 7811904 | Method of fabricating a semiconductor device employing electroless plating | Tao Feng, Ming Sun, Kai Liu | 2010-10-12 |
| 7633140 | Inverted J-lead for power devices | Leeshawn Luo, Anup Bhalla, Sik Lui, Mike F. Chang, Xiao Tiang Zhang | 2009-12-15 |
| 7595547 | Semiconductor die package including cup-shaped leadframe | Mike F. Chang, King Owyang, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu | 2009-09-29 |
| 7589396 | Chip scale surface mount package for semiconductor device and process of fabricating the same | Felix Zandman, Y. Mohammed Kasem | 2009-09-15 |
| 7391100 | Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area | Leeshawn Luo, Anup Bhalla, Sik Lui, Mike F. Chang | 2008-06-24 |
| 7211877 | Chip scale surface mount package for semiconductor device and process of fabricating the same | Felix Zandman, Y. Mohammed Kasem | 2007-05-01 |
| 7208818 | Power semiconductor package | Leeshawn Luo, Anup Bhalla, Sik Lui, Mike F. Chang, Xiao Zhang | 2007-04-24 |
| 7183616 | High speed switching MOSFETS using multi-parallel die packages with/without special leadframes | Anup Bhalla, Sik Lui, Leeshawn Luo | 2007-02-27 |
| 6909170 | Semiconductor assembly with package using cup-shaped lead-frame | Mike F. Chang, King Owyang, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu | 2005-06-21 |
| 6876061 | Chip scale surface mount package for semiconductor device and process of fabricating the same | Felix Zandman, Y. Mohammed Kasem | 2005-04-05 |
| 6841852 | Integrated circuit package for semiconductor devices with improved electric resistance and inductance | Leeshawn Luo, Anup Bhalla, Sik Lui, Mike F. Chang | 2005-01-11 |
| 6744124 | Semiconductor die package including cup-shaped leadframe | Mike F. Chang, King Owyang, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu | 2004-06-01 |
| 6562647 | Chip scale surface mount package for semiconductor device and process of fabricating the same | Felix Zandman, Y. Mohammed Kasem | 2003-05-13 |
| 6441475 | Chip scale surface mount package for semiconductor device and process of fabricating the same | Felix Zandman, Y. Mohammed Kasem | 2002-08-27 |
| 6392290 | Vertical structure for semiconductor wafer-level chip scale packages | Y. Mohammed Kasem, Lee Luo, Chang-Sheng Chen, Eddy Tjhia, Bosco Lan +2 more | 2002-05-21 |
| 6316287 | Chip scale surface mount packages for semiconductor device and process of fabricating the same | Felix Zandman, Y. Mohammed Kasem | 2001-11-13 |
| 6271060 | Process of fabricating a chip scale surface mount package for semiconductor device | Felix Zandman, Y. Mohammed Kasem | 2001-08-07 |
| 6249041 | IC chip package with directly connected leads | Y. Mohammed Kasem, Anthony C. Tsui, Lixiong Luo | 2001-06-19 |