Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8598035 | Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same | Michael D. Gruenhagen, Suku Kim, James J. Murphy, Chung-Lin Wu, Mark Larsen +1 more | 2013-12-03 |
| 8193043 | High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same | Oseob Jeon, Chung-Lin Wu, Bigildis Dosdos | 2012-06-05 |
| 8058732 | Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same | Michael D. Gruenhagen, Suku Kim, James J. Murphy, Ihsiu Ho, Chung-Lin Wu +2 more | 2011-11-15 |
| 7960800 | Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same | Michael D. Gruenhagen, Suku Kim, James J. Murphy, Chung-Lin Wu, Mark Larsen +1 more | 2011-06-14 |
| 7800219 | High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same | Oseob Jeon, Chung-Lin Wu, Bigildis Dosdos | 2010-09-21 |
| D472528 | Semiconductor chip package | Yehja Mohammed Kasem, Frank Kuo | 2003-04-01 |
| D466873 | Semiconductor chip package | Yehja Mohammed Kasem, Frank Kuo | 2002-12-10 |
| 6392290 | Vertical structure for semiconductor wafer-level chip scale packages | Y. Mohammed Kasem, Yueh-Se Ho, Lee Luo, Chang-Sheng Chen, Bosco Lan +2 more | 2002-05-21 |
| 5482819 | Photolithographic process for reducing repeated defects | Chi-Chan Lin, Anjali Anagol-Subbarao | 1996-01-09 |