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Metallization barrier structures for bonded integrated circuit interfaces |
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Backside source/drain replacement for semiconductor devices with metallization on both sides |
Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Patrick Morrow |
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Device layer interconnects |
Mark Bohr, Marni Nabors |
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| 11373999 |
Deep trench via for three-dimensional integrated circuit |
Yih Wang, Rishabh Mehandru, Tahir Ghani, Mark Bohr, Marni Nabors |
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| 11367796 |
Gate-all-around integrated circuit structures having asymmetric source and drain contact structures |
Biswajeet Guha, Tahir Ghani |
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Transistors with back-side contacts to create three dimensional memory and logic |
Wilfred Gomes, Abhishek A. Sharma, Tahir Ghani, Doug B. Ingerly, Rajesh Kumar |
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| 11329162 |
Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures |
Stephanie A. Bojarski, Myra McDonnell, Tahir Ghani |
2022-05-10 |
| 11328951 |
Transistor cells including a deep via lined wit h a dielectric material |
Patrick Morrow, Rishabh Mehandru |
2022-05-10 |
| 11276644 |
Integrated circuits and methods for forming thin film crystal layers |
Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek A. Sharma, Christopher J. Jezewski +1 more |
2022-03-15 |
| 11257822 |
Three-dimensional nanoribbon-based dynamic random-access memory |
Wilfred Gomes, Kinyip Phoa, Tahir Ghani, Uygar E. Avci, Rajesh Kumar |
2022-02-22 |
| 11239238 |
Thin film transistor based memory cells on both sides of a layer of logic devices |
Wilfred Gomes, Conor P. Puls, Kevin J. Fischer, Bernhard Sell, Abhishek A. Sharma +1 more |
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