Issued Patents 2022
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11522048 | Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs | Cory Bomberger, Anand S. Murthy, Tahir Ghani, Biswajeet Guha | 2022-12-06 |
| 11462536 | Integrated circuit structures having asymmetric source and drain structures | Anupama Bowonder, Rishabh Mehandru, Tahir Ghani | 2022-10-04 |
| 11437514 | Semiconductor device having tipless epitaxial source/drain regions | — | 2022-09-06 |
| 11410928 | Device layer interconnects | Mauro J. Kobrinsky, Marni Nabors | 2022-08-09 |
| 11387198 | Device, system and method for providing inductor structures | Wilfred Gomes, Doug B. Ingerly, Rajesh Kumar, Harish Krishnamurthy, Nachiket Desai | 2022-07-12 |
| 11373999 | Deep trench via for three-dimensional integrated circuit | Yih Wang, Rishabh Mehandru, Mauro J. Kobrinsky, Tahir Ghani, Marni Nabors | 2022-06-28 |
| 11373987 | Device, method and system for providing a stacked arrangement of integrated circuit dies | Wilfred Gomes, Glenn J. Hinton, Rajesh Kumar | 2022-06-28 |
| 11271010 | Multi version library cell handling and integrated circuit structures fabricated therefrom | Ranjith Kumar, Quan Shi, Andrew W. Yeoh, Sourav Chakravarty, Barbara A. Chappell +1 more | 2022-03-08 |
| 11257804 | Distributed semiconductor die and package architecture | Wilfred Gomes, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. Mc Cullough | 2022-02-22 |
| 11249113 | High density and fine pitch interconnect structures in an electric test apparatus | Pooya Tadayon, Joe Walczyk | 2022-02-15 |
| 11222863 | Techniques for die stacking and associated configurations | Fay Hua, Christopher M. Pelto, Valluri Rao, Johanna M. Swan | 2022-01-11 |