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Source and drain contact cut last process to enable wrap-around-contact |
Andrew M. Greene, Tenko Yamashita, Veeraraghavan S. Basker, Robert R. Robison, Ardasheir Rahman |
2020-11-17 |
| 10804368 |
Semiconductor device having two-part spacer |
Ruqiang Bao, Junli Wang, Heng Wu, Ernest Y. Wu |
2020-10-13 |
| 10797163 |
Leakage control for gate-all-around field-effect transistor devices |
Lan Yu, Heng Wu, Ruqiang Bao, Junli Wang |
2020-10-06 |
| 10692778 |
Gate-all-around FETs having uniform threshold voltage |
Ruqiang Bao, Junli Wang, Heng Wu |
2020-06-23 |
| 10685866 |
Fin isolation to mitigate local layout effects |
Huimei Zhou, Gen Tsutsui, Andrew M. Greene, Huiming Bu, Robert R. Robison +2 more |
2020-06-16 |
| 10664966 |
Anomaly detection using image-based physical characterization |
Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou |
2020-05-26 |
| 10658224 |
Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects |
Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Andrew M. Greene, Huiming Bu +1 more |
2020-05-19 |
| 10593802 |
Forming a sacrificial liner for dual channel devices |
Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu |
2020-03-17 |
| 10586700 |
Protection of low temperature isolation fill |
Michael P. Belyansky, Richard A. Conti, Devendra K. Sadana, Jay William Strane |
2020-03-10 |
| 10573646 |
Preserving channel strain in fin cuts |
Andrew M. Greene, Ravikumar Ramachandran, Rajasekhar Venigalla |
2020-02-25 |
| 10535517 |
Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS |
Choonghyun Lee, Ruqiang Bao, Gen Tsutsui |
2020-01-14 |
| 10535773 |
FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation |
Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh |
2020-01-14 |
| 10535550 |
Protection of low temperature isolation fill |
Michael P. Belyansky, Richard A. Conti, Devendra K. Sadana, Jay William Strane |
2020-01-14 |
