Issued Patents 2019
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522439 | Semiconductor package device | Nai-Wei Liu, Jing-Cheng Lin | 2019-12-31 |
| 10515930 | Three-layer package-on-package structure and method forming same | Feng-Cheng Hsu, Shin-Puu Jeng | 2019-12-24 |
| 10515875 | Interconnect structure for package-on-package devices | Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh +1 more | 2019-12-24 |
| 10510717 | Chip on package structure and method | Chen-Hua Yu, Der-Chyang Yeh, Kuo-Chung Yee | 2019-12-17 |
| 10504752 | Integrated passive device package and methods of forming same | Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng | 2019-12-10 |
| 10497619 | Method of manufacturing a semiconductor device including through silicon plugs | Chen-Hua Yu, Chia-Lin Yu, Hung-Pin Chang, Chien Ling Hwang, Yung-Chi Lin | 2019-12-03 |
| 10475769 | Semiconductor package and manufacturing method of the same | Feng-Cheng Hsu, Shin-Puu Jeng | 2019-11-12 |
| 10368442 | Integrated circuit structure and method of forming | Chen-Hua Yu, Kuo-Chung Yee | 2019-07-30 |
| 10354982 | Integrated fan-out structure with guiding trenches in buffer layer | Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jing-Cheng Lin | 2019-07-16 |
| 10276516 | Semiconductor package | Jing-Cheng Lin, Chin-Chuan Chang | 2019-04-30 |
| 10269685 | Interconnect structure for package-on-package devices | Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh +1 more | 2019-04-23 |
| 10269778 | Package on package (PoP) bonding structures | Jing-Cheng Lin, Po-Hao Tsai | 2019-04-23 |