TH

Terence B. Hook

IBM: 24 patents #127 of 11,143Top 2%
Overall (2019): #1,310 of 560,194Top 1%
24
Patents 2019

Issued Patents 2019

Patent #TitleCo-InventorsDate
10515859 Extra gate device for nanosheet Bruce B. Doris, Junli Wang 2019-12-24
10504889 Integrating a junction field effect transistor into a vertical field effect transistor Brent A. Anderson, Huiming Bu, Xuefeng Liu, Junli Wang 2019-12-10
10418462 Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process Brent A. Anderson, Huiming Bu, Fee Li Lie, Junli Wang 2019-09-17
10381346 Logic gate designs for 3D monolithic direct stacked VTFET Chen Zhang, Tenko Yamashita 2019-08-13
10366897 Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer Takashi Ando, Mohit Bajaj, Rajan K. Pandey, Rajesh Sathiyanarayanan 2019-07-30
10346580 Checking wafer-level integrated designs for rule compliance Larry Wissel 2019-07-09
10347494 Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer Takashi Ando, Mohit Bajaj, Rajan K. Pandey, Rajesh Sathiyanarayanan 2019-07-09
10340340 Multiple-threshold nanosheet transistors Ruqiang Bao, Michael A. Guillorn, Nicolas Loubet, Robert R. Robison, Reinaldo Vega +1 more 2019-07-02
10332959 Bulk to silicon on insulator device Joshua M. Rubin, Tenko Yamashita 2019-06-25
10326019 Fully-depleted CMOS transistors with U-shaped channel Kangguo Cheng, Robert H. Dennard, Bruce B. Doris 2019-06-18
10319596 Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer Takashi Ando, Mohit Bajaj, Rajan K. Pandey, Rajesh Sathiyanarayanan 2019-06-11
10283411 Stacked vertical transistor device for three-dimensional monolithic integration Joshua M. Rubin 2019-05-07
10276558 Electrostatic discharge protection using vertical fin CMOS technology Brent A. Anderson, Huiming Bu, Xuefeng Liu, Junli Wang, Miaomiao Wang 2019-04-30
10254340 Independently driving built-in self test circuitry over a range of operating conditions John Bradley Deforge, Theresa A. Newton, Kirk D. Peterson 2019-04-09
10249743 Semiconductor device with low band-to-band tunneling Nicolas Degors 2019-04-02
10249739 Nanosheet MOSFET with partial release and source/drain epitaxy Michael A. Guillorn, Nicolas Loubet, Robert R. Robison, Reinaldo Vega 2019-04-02
10248755 Checking wafer-level integrated designs for antenna rule compliance Larry Wissel 2019-04-02
10229915 Mirror contact capacitor Joshua M. Rubin, Tenko Yamashita 2019-03-12
10224327 Semiconductor device with different fin pitches Bruce B. Doris 2019-03-05
10211316 Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process Brent A. Anderson, Huiming Bu, Fee Li Lie, Junli Wang 2019-02-19
10204839 Prevention of charging damage in full-depletion devices 2019-02-12
10170576 Stable work function for narrow-pitch devices Takashi Ando, Mohit Bajaj, Rajan K. Pandey, Rajesh Sathiyanarayanan 2019-01-01
10170584 Nanosheet field effect transistors with partial inside spacers Michael A. Guillorn, Robert R. Robison, Reinaldo Vega, Rajasekhar Venigalla 2019-01-01
10170463 Bipolar transistor compatible with vertical FET fabrication Brent A. Anderson, Kangguo Cheng, Tak H. Ning 2019-01-01