Issued Patents 2017
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837440 | FinFET device with abrupt junctions | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo | 2017-12-05 |
| 9837535 | Directional deposition of protection layer | Juntao Li, Junli Wang, Chih-Chao Yang | 2017-12-05 |
| 9805992 | Strained finFET device fabrication | Bruce B. Doris, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg | 2017-10-31 |
| 9805991 | Strained finFET device fabrication | Bruce B. Doris, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg | 2017-10-31 |
| 9768272 | Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity | Pouya Hashemi, Alexander Reznicek, Tenko Yamashita | 2017-09-19 |
| 9768276 | Method and structure of forming FinFET electrical fuse structure | Juntao Li, Chih-Chao Yang, Yunpeng Yin | 2017-09-19 |
| 9761699 | Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures | Bruce B. Doris, Junli Wang, Nicolas Loubet | 2017-09-12 |
| 9728640 | Hybrid substrate engineering in CMOS finFET integration for mobility improvement | Chia-Yu Chen, Bruce B. Doris, Rajasekhar Venigalla | 2017-08-08 |
| 9728625 | Fin formation in fin field effect transistors | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Yunpeng Yin | 2017-08-08 |
| 9728534 | Densely spaced fins for semiconductor fin field effect transistors | Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2017-08-08 |
| 9728419 | Fin density control of multigate devices through sidewall image transfer processes | Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2017-08-08 |
| 9716045 | Directly forming SiGe fins on oxide | Kangguo Cheng, Juntao Li, Junli Wang | 2017-07-25 |
| 9716038 | Critical dimension shrink through selective metal growth on metal hardmask sidewalls | Hsueh-Chung Chen, Juntao Li, Chih-Chao Yang, Yunpeng Yin | 2017-07-25 |
| 9698098 | Anti-fuse structure and method for manufacturing the same | Juntao Li, Junli Wang, Chih-Chao Yang | 2017-07-04 |
| 9666527 | Middle of the line integrated eFuse in trench EPI structure | Juntao Li, Junli Wang, Chih-Chao Yang | 2017-05-30 |
| 9647092 | Method and structure of forming FinFET electrical fuse structure | Juntao Li, Chih-Chao Yang, Yunpeng Yin | 2017-05-09 |
| 9640641 | Silicon germanium fin channel formation | Nicolas Loubet, Junli Wang | 2017-05-02 |
| 9640640 | FinFET device with channel strain | Bruce B. Doris, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie | 2017-05-02 |
| 9634000 | Partially isolated fin-shaped field effect transistors | Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2017-04-25 |
| 9634117 | Self-aligned contact process enabled by low temperature | Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2017-04-25 |
| 9634027 | CMOS structure on SSOI wafer | Bruce B. Doris, Ali Khakifirooz, Junli Wang | 2017-04-25 |
| 9627263 | Stop layer through ion implantation for etch stop | Siva Kanakasabapathy, Yunpeng Yin, Chiahsun Tseng, Junli Wang | 2017-04-18 |
| 9614057 | Enriched, high mobility strained fin having bottom dielectric isolation | Bruce B. Doris, Juntao Li, Junli Wang, Chih-Chao Yang | 2017-04-04 |
| 9608067 | Hybrid aspect ratio trapping | Kangguo Cheng, Ramachandra Divakaruni, Juntao Li | 2017-03-28 |
| 9608068 | Substrate with strained and relaxed silicon regions | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2017-03-28 |