Issued Patents 2017
Showing 101–124 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9570299 | Formation of SiGe nanotubes | Kangguo Cheng, Hong He, Juntao Li | 2017-02-14 |
| 9564358 | Forming reliable contacts on tight semiconductor pitch | Xiuyu Cai, Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2017-02-07 |
| 9564486 | Self-aligned dual-height isolation for bulk FinFET | Murat Kerem Akarvardar, Steven Bentley, Kangguo Cheng, Bruce B. Doris, Jody A. Fronheiser +2 more | 2017-02-07 |
| 9564445 | Dummy gate structure for electrical isolation of a fin DRAM | John E. Barth, Jr., Kangguo Cheng, Bruce B. Doris, Herbert L. Ho, Babar A. Khan +4 more | 2017-02-07 |
| 9564443 | Dynamic random access memory cell with self-aligned strap | John E. Barth, Jr., Kangguo Cheng, Herbert L. Ho, Ravikumar Ramachandran, Kern Rim +1 more | 2017-02-07 |
| 9564439 | Structure and method for advanced bulk fin isolation | Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2017-02-07 |
| 9564373 | Forming a CMOS with dual strained channels | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-02-07 |
| 9564326 | Lithography using interface reaction | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-02-07 |
| 9559009 | Gate structure cut after formation of epitaxial active regions | Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Theodorus E. Standaert, Ruilong Xie | 2017-01-31 |
| 9559119 | High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process | Kangguo Cheng, Bruce B. Doris, Ghavam G. Shahidi | 2017-01-31 |
| 9559000 | Hybrid logic and SRAM contacts | Veeraraghavan S. Basker, Kangguo Cheng | 2017-01-31 |
| 9553032 | Fin field effect transistor including asymmetric raised active regions | Veeraraghavan S. Basker, Kangguo Cheng | 2017-01-24 |
| 9553015 | Fabrication of III-V-on-insulator platforms for semiconductor devices | Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi | 2017-01-24 |
| 9548356 | Shallow trench isolation structures | Bruce B. Doris, Kangguo Cheng, Balasubramanian S. Haran, Pranita Kerber, Arvind Kumar +1 more | 2017-01-17 |
| 9548386 | Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices | Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2017-01-17 |
| 9548385 | Self-aligned contacts for vertical field effect transistors | Kangguo Cheng, Wilfried E. Haensch, Davood Shahrjerdi | 2017-01-17 |
| 9548213 | Dielectric isolated fin with improved fin profile | Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Kern Rim | 2017-01-17 |
| 9543323 | Strain release in PFET regions | Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2017-01-10 |
| 9543440 | High density vertical nanowire stack for field effect transistor | Kangguo Cheng, Juntao Li | 2017-01-10 |
| 9543426 | Semiconductor devices with self-aligned contacts and low-k spacers | Ruilong Xie, Xiuyu Cai, Kangguo Cheng | 2017-01-10 |
| 9543302 | Forming IV fins and III-V fins on insulator | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2017-01-10 |
| 9536836 | MIS (Metal-Insulator-Semiconductor) contact structures for semiconductor devices | Ruilong Xie, Xiuyu Cai, Kangguo Cheng | 2017-01-03 |
| 9536979 | FinFET with reduced capacitance | Veeraraghavan S. Basker, Kangguo Cheng, Charles W. Koburger, III | 2017-01-03 |
| 9536877 | Methods of forming different spacer structures on integrated circuit products having differing gate pitch dimensions and the resulting products | Xiuyu Cai, Ruilong Xie, Kangguo Cheng | 2017-01-03 |