Issued Patents 2016
Showing 26–34 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9305769 | Thin wafer handling method | Chen-Hua Yu, Wen-Chih Chiou, Hung-Jung Tu | 2016-04-05 |
| 9299676 | Through silicon via structure | Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai | 2016-03-29 |
| 9299649 | 3D packages and methods for forming the same | Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou | 2016-03-29 |
| 9293369 | Three-dimensional integrated circuit (3DIC) | Chih-Wei Wu, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu | 2016-03-22 |
| 9281297 | Solution for reducing poor contact in info packages | Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih-Ting Lin | 2016-03-08 |
| 9275948 | Integrated circuit having stress tuning layer | Clinton Chao, Szu-Wei Lu | 2016-03-01 |
| 9269694 | Packages with thermal management features for reduced thermal crosstalk and methods of forming same | Kim Hong Chen, Wensen Hung, Szu-Po Huang | 2016-02-23 |
| 9240349 | Interconnect structures for substrate | Chen-Hua Yu, Wen-Chih Chiou, Tsang-Jiuh Wu | 2016-01-19 |
| 9230902 | Interconnect structure for wafer level package | Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung | 2016-01-05 |