Issued Patents 2005
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6977194 | Structure and method to improve channel mobility by gate electrode stress modification | Michael P. Belyansky, Dureseti Chidambarrao, Omer H. Dokumaci, Bruce B. Doris | 2005-12-20 |
| 6975133 | Logic circuits having linear and cellular gate transistors | Victor Wing Chung Chan, Hsing-Jen Wann, Shih-Fen Huang | 2005-12-13 |
| 6974991 | DRAM cell with buried collar and self-aligned buried strap | Kangguo Cheng, Ramachandra Divkaruni, Gary B. Bronner, Carl Radens | 2005-12-13 |
| 6960514 | Pitcher-shaped active area for field effect transistor and method of forming same | Jochen Beintner, Rama Divakaruni, Johnathan E. Faltermeier, Philip L. Flaitz, Carol J. Heenan +5 more | 2005-11-01 |
| 6933577 | High performance FET with laterally thin extension | Cyril Cabral, Jr., Omer H. Dokumaci | 2005-08-23 |
| 6930060 | Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric | Anthony I. Chou, Michael P. Chudzik, Toshiharu Furukawa, Paul Kirsch, Kristen Scheer +1 more | 2005-08-16 |
| 6911384 | Gate structure with independently tailored vertical doping profile | Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman, Carl Radens | 2005-06-28 |
| 6908806 | Gate metal recess for oxidation protection and parasitic capacitance reduction | Haining Yang, Ramachandra Divakaruni, Rajeev Malik, Hongwen Yan, Ravikumar Ramachandran | 2005-06-21 |
| 6891192 | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Huajie Chen, Dureseti Chidambarrao, An Steegen, Haining Yang | 2005-05-10 |
| 6890833 | Trench isolation employing a doped oxide trench fill | Michael P. Belyansky, Andreas Knorr, Christopher C. Parks | 2005-05-10 |
| 6878582 | Low-GIDL MOSFET structure and method for fabrication | Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman, Carl Radens | 2005-04-12 |
| 6873010 | High performance logic and high density embedded dram with borderless contact and antispacer | Dureseti Chidambarrao, Omer H. Dokumaci, Bruce B. Doris, Rajarao Jammy, Jack A. Mandelman | 2005-03-29 |
| 6841826 | Low-GIDL MOSFET structure and method for fabrication | Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman, Carl Radens | 2005-01-11 |
| 6838334 | Method of fabricating a buried collar | Chung-Yung Sung, Helmut Tews | 2005-01-04 |