Issued Patents 2005
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6967137 | Forming collar structures in deep trench capacitors with thermally stable filler material | Michael P. Belyansky, Jack A. Mandelman, Dae-Gyu Park | 2005-11-22 |
| 6964892 | N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same | Lawrence A. Clevenger, Louis L. Hsu, Yujun Li | 2005-11-15 |
| 6962872 | High density chip carrier with integrated passive devices | Michael P. Chudzik, Robert H. Dennard, Bruce K. Furman, Rajarao Jammy, Chandrasekhar Narayan +3 more | 2005-11-08 |
| 6960514 | Pitcher-shaped active area for field effect transistor and method of forming same | Jochen Beintner, Johnathan E. Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan +5 more | 2005-11-01 |
| 6940149 | Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base | Gregory G. Freeman, Marwan H. Khater, William R. Tonti | 2005-09-06 |
| 6897107 | Method for forming TTO nitride liner for improved collar protection and TTO reliability | Thomas W. Dyer, Rajeev Malik, Jack A. Mandelman, Venkatachajam C. Jaiprakash | 2005-05-24 |
| 6890815 | Reduced cap layer erosion for borderless contacts | Johnathan E. Faltermeier, Jeremy K. Stephens, David M. Dobuzinsky, Larry Clevenger, Munir D. Naeem +3 more | 2005-05-10 |
| 6870211 | Self-aligned array contact for memory cells | Johnathan E. Faltermeier, Michael Maldei, Jay William Strane | 2005-03-22 |
| 6869860 | Filling high aspect ratio isolation structures with polysilazane based material | Michael P. Belyansky, Laertis Economikos, Rajarao Jammy, Kenneth Settlemeyer, Padraic Shafer | 2005-03-22 |
| 6864540 | High performance FET with elevated source/drain region | Louis C. Hsu, Rajiv V. Joshi, Carl Radens | 2005-03-08 |