Issued Patents 2005
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979851 | Structure and method of vertical transistor DRAM cell having a low leakage buried strap | Dureseti Chidambarrao, Jack A. Mandelman | 2005-12-27 |
| 6974991 | DRAM cell with buried collar and self-aligned buried strap | Kangguo Cheng, Ramachandra Divkaruni, Gary B. Bronner, Oleg Gluschenkov | 2005-12-13 |
| 6958522 | Method to fabricate passive components using conductive polymer | Lawrence A. Clevenger, Louis L. Hsu, Li-Kong Wang, Kwong Hon Wong | 2005-10-25 |
| 6943409 | Trench optical device | Kangguo Cheng, Ramachandra Divakaruni | 2005-09-13 |
| 6936512 | Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric | Michael P. Chudzik, Rajarao Jammy, Kenneth T. Settlemyer, Jr., Padraic Shafer, Joseph F. Shepard, Jr. | 2005-08-30 |
| 6933189 | Integration system via metal oxide conversion | Lawrence A. Clevenger, Louis L. Hsu, Joseph F. Shepard, Jr. | 2005-08-23 |
| 6911384 | Gate structure with independently tailored vertical doping profile | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman | 2005-06-28 |
| 6888215 | Dual damascene anti-fuse with via before wire | Axel Brintzinger | 2005-05-03 |
| 6887785 | Etching openings of different depths using a single mask layer method and structure | David M. Dobuzinsky, Roy Iggulden, Jay William Strane, Keith Kwong Hon Wong | 2005-05-03 |
| 6884715 | Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby | Oh-Jung Kwon, Kangguo Cheng, Deok-kee Kim | 2005-04-26 |
| 6882027 | Methods and apparatus for providing an antifuse function | Axel Brintzinger, William R. Tonti | 2005-04-19 |
| 6878582 | Low-GIDL MOSFET structure and method for fabrication | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman | 2005-04-12 |
| 6869895 | Method for adjusting capacitance of an on-chip capacitor | Lawrence A. Clevenger, Timothy J. Dalton, Louis L. Hsu, Keith Kwong Hon Wong, Chih-Chao Yang | 2005-03-22 |
| 6869846 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Jack A. Mandelman, Richard Strub, William R. Tonti | 2005-03-22 |
| 6864540 | High performance FET with elevated source/drain region | Rama Divakaruni, Louis C. Hsu, Rajiv V. Joshi | 2005-03-08 |
| 6841826 | Low-GIDL MOSFET structure and method for fabrication | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman | 2005-01-11 |