Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979851 | Structure and method of vertical transistor DRAM cell having a low leakage buried strap | Dureseti Chidambarrao, Carl Radens | 2005-12-27 |
| 6974743 | Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates | Ramac Divakaruni, Stephan Kudelka | 2005-12-13 |
| 6972220 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, William R. Tonti | 2005-12-06 |
| 6967137 | Forming collar structures in deep trench capacitors with thermally stable filler material | Michael P. Belyansky, Rama Divakaruni, Dae-Gyu Park | 2005-11-22 |
| 6911687 | Buried bit line-field isolation defined active semiconductor areas | Gerhard Kunkel | 2005-06-28 |
| 6909137 | Method of creating deep trench capacitor using a P+ metal electrode | Ramachandra Divakaruni, Dae-Gyu Park | 2005-06-21 |
| 6897107 | Method for forming TTO nitride liner for improved collar protection and TTO reliability | Rama Divakaruni, Thomas W. Dyer, Rajeev Malik, Venkatachajam C. Jaiprakash | 2005-05-24 |
| 6872620 | Trench capacitors with reduced polysilicon stress | Dureseti Chidambarrao, Rajarao Jammy | 2005-03-29 |
| 6869846 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Carl Radens, Richard Strub, William R. Tonti | 2005-03-22 |