Issued Patents 2005
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979851 | Structure and method of vertical transistor DRAM cell having a low leakage buried strap | Jack A. Mandelman, Carl Radens | 2005-12-27 |
| 6977194 | Structure and method to improve channel mobility by gate electrode stress modification | Michael P. Belyansky, Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov | 2005-12-20 |
| 6974981 | Isolation structures for imposing stress patterns | Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman | 2005-12-13 |
| 6972461 | Channel MOSFET with strained silicon channel on strained SiGe | Xiangdong Chen, Geng Wang, Huilong Zhu | 2005-12-06 |
| 6967384 | Structure and method for ultra-small grain size polysilicon | Jochen Beintner | 2005-11-22 |
| 6930004 | Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling | Geng Wang, Kevin McStay, Mary E. Weybright, Yujun Li | 2005-08-16 |
| 6906360 | Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions | Huajie Chen, Omer Dokumaci, Haining Yang | 2005-06-14 |
| 6890808 | Method and structure for improved MOSFETs using poly/silicide gate height control | Omer H. Dokumaci | 2005-05-10 |
| 6891192 | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Huajie Chen, Oleg Gluschenkov, An Steegen, Haining Yang | 2005-05-10 |
| 6887751 | MOSFET performance improvement using deformation in SOI structure | Omer H. Dokumaci | 2005-05-03 |
| 6884667 | Field effect transistor with stressed channel and method for making same | Bruce B. Doris, Xavier Baie, Jack A. Mandelman, Devendra K. Sadana, Dominic J. Schepis | 2005-04-26 |
| 6881635 | Strained silicon NMOS devices with embedded source/drain | Effendi Leobandung, Anda C. Mocuta, Haining Yang, Huilong Zhu | 2005-04-19 |
| 6878978 | CMOS performance enhancement using localized voids and extended defects | Omer H. Dokumaci, Suryanarayan G. Hegde | 2005-04-12 |
| 6873010 | High performance logic and high density embedded dram with borderless contact and antispacer | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Rajarao Jammy, Jack A. Mandelman | 2005-03-29 |
| 6872641 | Strained silicon on relaxed sige film with uniform misfit dislocation density | Omer H. Dokumaci | 2005-03-29 |
| 6872620 | Trench capacitors with reduced polysilicon stress | Rajarao Jammy, Jack A. Mandelman | 2005-03-29 |
| 6869866 | Silicide proximity structures for CMOS device performance improvements | Omer H. Dokumaci, Rajesh Rengarajan, An Steegen | 2005-03-22 |
| 6858488 | CMOS performance enhancement using localized voids and extended defects | Omer H. Dokumaci, Suryanarayan G. Hegde | 2005-02-22 |