Issued Patents 2005
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6960523 | Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device | Michael Maldei, Prakash Dev, David M. Dobuzinsky, Johnathan E. Faltermeier, Thomas Rupp +3 more | 2005-11-01 |
| 6960818 | Recessed shallow trench isolation structure nitride liner and method for making same | Venkatachalam C. Jaiprakash | 2005-11-01 |
| 6869866 | Silicide proximity structures for CMOS device performance improvements | Dureseti Chidambarrao, Omer H. Dokumaci, An Steegen | 2005-03-22 |
| 6867087 | Formation of dual work function gate electrode | Kilho Lee, Woo-Tang Kang | 2005-03-15 |