Issued Patents 2005
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6974736 | Method of forming FET silicide gate structures incorporating inner spacers | Victor Ku, Hsing-Jen Wann, Keith Kwong Hon Wong | 2005-12-13 |
| 6936522 | Selective silicon-on-insulator isolation structure and method | Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach, Robert C. Wong | 2005-08-30 |
| 6927117 | Method for integration of silicide contacts and silicide gate metals | Cyril Cabral, Jr., Jakub Kedzierski, Victor Ku, Christian Lavoie, Vijay Narayanan | 2005-08-09 |
| 6921711 | Method for forming metal replacement gate of high performance | Cyril Cabral, Jr., Paul C. Jamison, Victor Ku, Ying Li, Vijay Narayanan +2 more | 2005-07-26 |
| 6891192 | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Huajie Chen, Dureseti Chidambarrao, Oleg Gluschenkov, Haining Yang | 2005-05-10 |
| 6876040 | Dense SRAM cells with selective SOI | Hsingjen Wann, Ying Zhang, Robert C. Wong | 2005-04-05 |
| 6869866 | Silicide proximity structures for CMOS device performance improvements | Dureseti Chidambarrao, Omer H. Dokumaci, Rajesh Rengarajan | 2005-03-22 |