Issued Patents 2005
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6972247 | Method of fabricating strained Si SOI wafers | Stephen W. Bedell, Guy M. Cohen | 2005-12-06 |
| 6958286 | Method of preventing surface roughening during hydrogen prebake of SiGe substrates | Dan M. Mocuta, Richard J. Murphy, Stephan W. Bedell, Devendra K. Sadana | 2005-10-25 |
| 6924517 | Thin channel FET with recessed source/drains and extensions | Bruce B. Doris, Philip J. Oldiges, Xinlin Wang, Huilong Zhu | 2005-08-02 |
| 6916698 | High performance CMOS device structure with mid-gap metal gate | Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta | 2005-07-12 |
| 6906360 | Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions | Dureseti Chidambarrao, Omer Dokumaci, Haining Yang | 2005-06-14 |
| 6893936 | Method of Forming strained SI/SIGE on insulator with silicon germanium buffer | Stephen W. Bedell | 2005-05-17 |
| 6891192 | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Dureseti Chidambarrao, Oleg Gluschenkov, An Steegen, Haining Yang | 2005-05-10 |
| 6844225 | Self-aligned mask formed utilizing differential oxidation rates of materials | Kathryn T. Schonenberg, Gregory G. Freeman, Andreas D. Stricker, Jae-Sung Rieh | 2005-01-18 |