Issued Patents 2005
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6972247 | Method of fabricating strained Si SOI wafers | Stephen W. Bedell, Huajie Chen | 2005-12-06 |
| 6972250 | Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device | Cyril Cabral, Jr., Roy A. Carruthers, Kevin K. Chan, Jack O. Chu, Steven J. Koester +2 more | 2005-12-06 |
| 6967377 | Double-gate fet with planarized surfaces and self-aligned silicides | Hon-Sum Philip Wong | 2005-11-22 |
| 6963505 | Method circuit and system for determining a reference voltage | — | 2005-11-08 |
| 6946696 | Self-aligned isolation double-gate FET | Kevin K. Chan, Meikei Ieong, Ronnen Andrew Roy, Paul M. Solomon, Min Yang | 2005-09-20 |