Issued Patents 2005
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6972250 | Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device | Cyril Cabral, Jr., Roy A. Carruthers, Jack O. Chu, Guy M. Cohen, Steven J. Koester +2 more | 2005-12-06 |
| 6946696 | Self-aligned isolation double-gate FET | Guy M. Cohen, Meikei Ieong, Ronnen Andrew Roy, Paul M. Solomon, Min Yang | 2005-09-20 |
| 6927454 | Split poly-SiGe/poly-Si alloy gate stack | Jia Chen, Shih-Fen Huang, Edward J. Nowak | 2005-08-09 |
| 6916694 | Strained silicon-channel MOSFET using a damascene gate process | Hussein I. Hanafi, David J. Frank | 2005-07-12 |
| 6893948 | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size | Arne Ballantine, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan +3 more | 2005-05-17 |
| 6891231 | Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier | Nestor A. Bojarczuk, Christopher P. D'Emic, Evgeni Gousev, Supratik Guha, Paul C. Jamison +1 more | 2005-05-10 |
| 6891227 | Self-aligned nanotube field effect transistor and method of fabricating same | Joerg Appenzeller, Phaedon Avouris, Richard Martel, Hon-Sum Philip Wong, Philip G. Collins | 2005-05-10 |
| 6870232 | Scalable MOS field effect transistor | Jack O. Chu, Khalid EzzEldin Ismail, Stephen A. Rishton, Katherine L. Saenger | 2005-03-22 |
| 6841831 | Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process | Hussein I. Hanafi, Diane C. Boyd, Wesley C. Natzle, Leathen Shi | 2005-01-11 |
| 6838695 | CMOS device structure with improved PFET gate electrode | Bruce B. Doris, Ashima B. Chakravarti, Daniel A. Uriarte | 2005-01-04 |