Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6960510 | Method of making sub-lithographic features | Sadanand V. Deshpande, Toshiharu Furukawa, David V. Horak, Akihisa Sekiguchi, Len Yuan Tsou +1 more | 2005-11-01 |
| 6926843 | Etching of hard masks | Marc W. Cantell, Steven Ruegsegger | 2005-08-09 |
| 6905941 | Structure and method to fabricate ultra-thin Si channel devices | Bruce B. Doris, Thomas S. Kanarsky, Meikei Ieong | 2005-06-14 |
| 6884734 | Vapor phase etch trim structure with top etch blocking layer | Frederick Buehrer, Derek Chen, William Chu, Scott W. Crowder, Sadanand V. Deshpande +4 more | 2005-04-26 |
| 6858903 | MOSFET device with in-situ doped, raised source and drain structures | Marc W. Cantell, Louis D. Lanzerotti, Effendi Leobandung, Brian L. Tessier, Ryan Wuthrich | 2005-02-22 |
| 6858532 | Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling | David C. Ahlgren, Steven G. Barbee, Marc W. Cantell, Basanth Jagannathan, Louis D. Lanzerotti +2 more | 2005-02-22 |
| 6849153 | Removal of post-rie polymer on A1/CU metal line | Ravikumar Ramachandran, Martin Gutsche, Hiroyuki Akatsu, Chien-Yi Yu | 2005-02-01 |
| 6841831 | Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process | Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Leathen Shi | 2005-01-11 |
| 6838347 | Method for reducing line edge roughness of oxide material using chemical oxide removal | Joyce C. Liu, Richard S. Wise, Hongwen Yan, Bidan Zhang | 2005-01-04 |