Issued Patents 2002
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6497800 | Device providing electrical contact to the surface of a semiconductor workpiece during metal plating | Homayoun Talieh, Bulent M. Basol | 2002-12-24 |
| 6492262 | Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies | — | 2002-12-10 |
| 6482307 | Method of and apparatus for making electrical contact to wafer surface for full-face electroplating or electropolishing | Jalal Ashjaee, Boguslaw Nagorski, Bulent M. Basol, Homayoun Talieh | 2002-11-19 |
| 6478936 | Anode assembly for plating and planarizing a conductive layer | Rimma Volodarsky, Konstantin Volodarsky, Homayoun Talieh, Douglas W. Young | 2002-11-12 |
| 6465376 | Method and structure for improving electromigration of chip interconnects | Daniel C. Edelstein, Andrew H. Simon | 2002-10-15 |
| 6437440 | Thin film metal barrier for electrical interconnections | Cyril Cabral, Jr., Patrick W. DeHaven, Daniel C. Edelstein, David P. Klaus, James Manley Pollard, III +1 more | 2002-08-20 |
| 6429519 | Wiring structures containing interconnected metal and wiring levels including a continuous, single crystalline or polycrystalline conductive material having one or more twin boundaries | — | 2002-08-06 |
| 6413403 | Method and apparatus employing pad designs and structures with improved fluid distribution | Paul Lindquist, Bulent M. Basol, Homayoun Talieh | 2002-07-02 |
| 6413854 | Method to build multi level structure | Daniel C. Edelstein, Cheryl G. Faltermeier, Peter S. Locke | 2002-07-02 |
| 6413388 | Pad designs and structures for a versatile materials processing apparatus | Bulent M. Basol, Homayoun Talieh | 2002-07-02 |
| 6409904 | Method and apparatus for depositing and controlling the texture of a thin film | Homayoun Talieh | 2002-06-25 |
| 6406608 | Apparatus to monitor and add plating solution to plating baths and controlling quality of deposited metal | Wilma Jean Horkans, Panayotis Andricacos | 2002-06-18 |
| 6399496 | Copper interconnection structure incorporating a metal seed layer | Daniel C. Edelstein, James M. E. Harper, Chao-Kun Hu, Andrew H. Simon | 2002-06-04 |
| 6380628 | Microstructure liner having improved adhesion | John A. Miller, Andrew H. Simon, Jill Slattery, Yun-Yu Wang | 2002-04-30 |
| 6372081 | Process to prevent copper contamination of semiconductor fabs | L. Paivikki Buchwalter | 2002-04-16 |
| 6355153 | Chip interconnect and packaging deposition methods and structures | Homayoun Talieh, Bulent M. Basol | 2002-03-12 |
| 6354916 | Modified plating solution for plating and planarization and process utilizing same | Bulent M. Basol, Homayoun Talieh | 2002-03-12 |
| 6352623 | Vertically configured chamber used for multiple processes | Konstantin Volodarsky, Boguslaw Nagorski, Rimma Volodarsky, Douglas W. Young, Homayoun Talieh | 2002-03-05 |
| 6344129 | Method for plating copper conductors and devices formed | Kenneth P. Rodbell, Panayotis Andricacos, Cyril Cabral, Jr., Lynne M. Gignac, Peter S. Locke | 2002-02-05 |
| 6339258 | Low resistivity tantalum | Edward C. Cooney, III | 2002-01-15 |
| 6337218 | Method to test devices on high performance ULSI wafers | Stephen A. Cohen, Arnold Halperin | 2002-01-08 |
| 6337151 | Graded composition diffusion barriers for chip wiring applications | Daniel C. Edelstein, Andrew H. Simon | 2002-01-08 |