Issued Patents 2002
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6489207 | Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor | Toshiharu Furukawa, Mark C. Hakey, David V. Horak | 2002-12-03 |
| 6452265 | Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Rosemary A. Previti-Kelly, Edmund J. Sprogis | 2002-09-17 |
| 6444402 | Method of making differently sized vias and lines on the same lithography level | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, William H. Ma | 2002-09-03 |
| 6440635 | Low “K” factor hybrid photoresist | Ahmad D. Katnani, Niranjan M. Patel, Paul A. Rabidoux | 2002-08-27 |
| 6441464 | Gate oxide stabilization by means of germanium components in gate conductor | Mark C. Hakey, Toshiharu Furukawa, David V. Horak | 2002-08-27 |
| 6440801 | Structure for folded architecture pillar memory cell | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Howard L. Kalter, Jack A. Mandelman +2 more | 2002-08-27 |
| 6429045 | Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, H. Bernhard Pogge, Edmund J. Sprogis +1 more | 2002-08-06 |
| 6420766 | Transistor having raised source and drain | Jeffrey S. Brown, James S. Dunn, David V. Horak, Robert K. Leidy, Steven H. Voldman | 2002-07-16 |
| 6391426 | High capacitance storage node structures | Mark C. Hakey, David V. Horak, William H. Ma | 2002-05-21 |
| 6387783 | Methods of T-gate fabrication using a hybrid resist | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Paul A. Rabidoux | 2002-05-14 |
| 6376873 | Vertical DRAM cell with robust gate-to-storage node isolation | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Thomas S. Kanarsky, Jeffrey J. Welser | 2002-04-23 |
| 6372412 | Method of producing an integrated circuit chip using frequency doubling hybrid photoresist and apparatus formed thereby | Mark C. Hakey, David V. Horak, Ahmad D. Katnani, Niranjan M. Patel, Paul A. Rabidoux | 2002-04-16 |
| 6369397 | SPM base focal plane positioning | Brent A. Anderson, James A. Bruce, Peter H. Mitchell, Robert A. Myers | 2002-04-09 |
| 6358813 | Method for increasing the capacitance of a semiconductor capacitors | Charles T. Black, David J. Frank, Toshiharu Furukawa, Mark C. Hakey, David V. Horak +3 more | 2002-03-19 |
| 6344416 | Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions | Toshiharu Furukawa, Mark C. Hakey, David V. Horak | 2002-02-05 |
| 6342323 | Alignment methodology for lithography | William H. Ma, David V. Horak, Toshiharu Furukawa, Mark C. Hakey | 2002-01-29 |
| 6342735 | Dual use alignment aid | James J. Colelli, Peter H. Mitchell, Joseph Mundenar, Charles A. Whiting | 2002-01-29 |
| 6338934 | Hybrid resist based on photo acid/photo base blending | Kuang-Jung Chen, Mark C. Hakey, Wu-Song Huang, Paul A. Rabidoux | 2002-01-15 |