Issued Patents 2002
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6489207 | Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes | 2002-12-03 |
| 6452265 | Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Rosemary A. Previti-Kelly, Edmund J. Sprogis | 2002-09-17 |
| 6444402 | Method of making differently sized vias and lines on the same lithography level | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, William H. Ma | 2002-09-03 |
| 6441464 | Gate oxide stabilization by means of germanium components in gate conductor | Steven J. Holmes, Mark C. Hakey, Toshiharu Furukawa | 2002-08-27 |
| 6440801 | Structure for folded architecture pillar memory cell | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Howard L. Kalter, Jack A. Mandelman +2 more | 2002-08-27 |
| 6436814 | Interconnection structure and method for fabricating same | William A. Klaasen, Thomas L. McDevitt, Mark P. Murray, Anthony K. Stamper | 2002-08-20 |
| 6429080 | Multi-level dram trench store utilizing two capacitors and two plates | Toshiharu Furukawa, Howard L. Kalter | 2002-08-06 |
| 6429045 | Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, H. Bernhard Pogge, Edmund J. Sprogis +1 more | 2002-08-06 |
| 6426175 | Fabrication of a high density long channel DRAM gate with or without a grooved gate | Toshiharu Furukawa, Mark C. Hakey, Stevn J. Holmes, Paul A. Rabidoux | 2002-07-30 |
| 6426558 | Metallurgy for semiconductor devices | Jonathan D. Chapple-Sokol, Paul M. Feeney, Robert M. Geffken, Mark P. Murray, Anthony K. Stamper | 2002-07-30 |
| 6420748 | Borderless bitline and wordline DRAM structure | Mark C. Hakey, William H. Ma, Wendell P. Noble | 2002-07-16 |
| 6391426 | High capacitance storage node structures | Mark C. Hakey, Steven J. Holmes, William H. Ma | 2002-05-21 |
| 6387783 | Methods of T-gate fabrication using a hybrid resist | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Paul A. Rabidoux | 2002-05-14 |
| 6376873 | Vertical DRAM cell with robust gate-to-storage node isolation | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Thomas S. Kanarsky, Jeffrey J. Welser | 2002-04-23 |
| 6373091 | Vertical DRAM cell with TFT over trench capacitor | Rick L. Mohler, Gorden Seth Starkey, Jr. | 2002-04-16 |
| 6372412 | Method of producing an integrated circuit chip using frequency doubling hybrid photoresist and apparatus formed thereby | Mark C. Hakey, Steven J. Holmes, Ahmad D. Katnani, Niranjan M. Patel, Paul A. Rabidoux | 2002-04-16 |
| 6358813 | Method for increasing the capacitance of a semiconductor capacitors | Steven J. Holmes, Charles T. Black, David J. Frank, Toshiharu Furukawa, Mark C. Hakey +3 more | 2002-03-19 |
| 6344416 | Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes | 2002-02-05 |
| 6342722 | Integrated circuit having air gaps between dielectric and conducting lines | Michael D. Armacost, Peter D. Hoh, Richard S. Wise | 2002-01-29 |