Issued Patents 2002
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6498739 | Applications for non-volatile memory cells | Eugene H. Cloud | 2002-12-24 |
| 6498065 | Memory address decode array with vertical transistors | Leonard Forbes | 2002-12-24 |
| 6492694 | Highly conductive composite polysilicon gate for CMOS integrated circuits | Leonard Forbes | 2002-12-10 |
| 6492233 | Memory cell with vertical transistor and buried word and body lines | Leonard Forbes, Kie Y. Ahn | 2002-12-10 |
| 6489192 | Base current reversal SRAM memory cell and method | — | 2002-12-03 |
| 6486027 | Field programmable logic arrays with vertical transistors | Leonard Forbes | 2002-11-26 |
| 6486703 | Programmable logic array with vertical transistors | Leonard Forbes | 2002-11-26 |
| 6483171 | Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same | Leonard Forbes, Alan R. Reinberg | 2002-11-19 |
| 6476434 | 4 F2 folded bit line dram cell structure having buried bit and word lines | Leonard Forbes, Kie Y. Ahn | 2002-11-05 |
| 6477080 | Circuits and methods for a static random access memory using vertical transistors | — | 2002-11-05 |
| 6472263 | Negative resistance memory cell and method | — | 2002-10-29 |
| 6461926 | Circuit and method for a memory cell using reverse base current effect | — | 2002-10-08 |
| 6452856 | DRAM technology compatible processor/memory chips | Leonard Forbes, Eugene H. Cloud | 2002-09-17 |
| 6448615 | Methods, structures, and circuits for transistors with gate-to-body capacitive coupling | Leonard Forbes | 2002-09-10 |
| 6449186 | Circuits and methods for a static random access memory using vertical transistors | — | 2002-09-10 |
| 6436748 | Method for fabricating CMOS transistors having matching characteristics and apparatus formed thereby | Leonard Forbes | 2002-08-20 |
| 6420748 | Borderless bitline and wordline DRAM structure | Mark C. Hakey, David V. Horak, William H. Ma | 2002-07-16 |
| 6417040 | Method for forming memory array having a digit line buried in an isolation region | — | 2002-07-09 |
| 6414356 | Circuits and methods for dual-gated transistors | Leonard Forbes | 2002-07-02 |
| 6403429 | SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY | — | 2002-06-11 |
| 6399979 | Memory cell having a vertical transistor with buried source/drain and dual gates | Leonard Forbes, Kie Y. Ahn | 2002-06-04 |
| 6395597 | Trench DRAM cell with vertical device and buried word lines | — | 2002-05-28 |
| 6383871 | Method of forming multiple oxide thicknesses for merged memory and logic applications | Leonard Forbes | 2002-05-07 |
| 6380581 | DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors | Eugene H. Cloud | 2002-04-30 |
| 6376317 | Methods for dual-gated transistors | Leonard Forbes | 2002-04-23 |