Issued Patents 2002
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6489207 | Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor | Mark C. Hakey, Steven J. Holmes, David V. Horak | 2002-12-03 |
| 6452265 | Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion | Mark C. Hakey, Steven J. Holmes, David V. Horak, Rosemary A. Previti-Kelly, Edmund J. Sprogis | 2002-09-17 |
| 6444402 | Method of making differently sized vias and lines on the same lithography level | Mark C. Hakey, Steven J. Holmes, David V. Horak, William H. Ma | 2002-09-03 |
| 6441464 | Gate oxide stabilization by means of germanium components in gate conductor | Steven J. Holmes, Mark C. Hakey, David V. Horak | 2002-08-27 |
| 6440801 | Structure for folded architecture pillar memory cell | Mark C. Hakey, Steven J. Holmes, David V. Horak, Howard L. Kalter, Jack A. Mandelman +2 more | 2002-08-27 |
| 6429045 | Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage | Mark C. Hakey, Steven J. Holmes, David V. Horak, H. Bernhard Pogge, Edmund J. Sprogis +1 more | 2002-08-06 |
| 6429080 | Multi-level dram trench store utilizing two capacitors and two plates | David V. Horak, Howard L. Kalter | 2002-08-06 |
| 6426175 | Fabrication of a high density long channel DRAM gate with or without a grooved gate | Mark C. Hakey, Stevn J. Holmes, David V. Horak, Paul A. Rabidoux | 2002-07-30 |
| 6426305 | Patterned plasma nitridation for selective epi and silicide formation | Anthony I. Chou, Akihisa Sekiguchi | 2002-07-30 |
| 6417515 | In-situ ion implant activation and measurement apparatus | Howard T. Barrett, John J. Ellis-Monaghan, James A. Slinkman | 2002-07-09 |
| 6396120 | Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application | Claude L. Bertin, Erik L. Hedberg, Jack A. Mandelman, William R. Tonti, Richard Q. Williams | 2002-05-28 |
| 6387783 | Methods of T-gate fabrication using a hybrid resist | Mark C. Hakey, Steven J. Holmes, David V. Horak, Paul A. Rabidoux | 2002-05-14 |
| 6380027 | Dual tox trench dram structures and process using V-groove | Jeffrey P. Gambino, Edward W. Kiewra, Jack A. Mandelman, Carl Radens, William R. Tonti +1 more | 2002-04-30 |
| 6376873 | Vertical DRAM cell with robust gate-to-storage node isolation | Mark C. Hakey, Steven J. Holmes, David V. Horak, Thomas S. Kanarsky, Jeffrey J. Welser | 2002-04-23 |
| 6358813 | Method for increasing the capacitance of a semiconductor capacitors | Steven J. Holmes, Charles T. Black, David J. Frank, Mark C. Hakey, David V. Horak +3 more | 2002-03-19 |
| 6344416 | Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions | Mark C. Hakey, Steven J. Holmes, David V. Horak | 2002-02-05 |
| 6342323 | Alignment methodology for lithography | William H. Ma, David V. Horak, Steven J. Holmes, Mark C. Hakey | 2002-01-29 |