Issued Patents 2002
Showing 1–25 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501117 | Static self-refreshing DRAM structure and operating mode | Carl Radens, Gary B. Bronner, Ramachandra Divakaruni | 2002-12-31 |
| 6501131 | Transistors having independently adjustable parameters | Rama Divakaruni, Jeffrey P. Gambino, Rajesh Rengarajan | 2002-12-31 |
| 6498518 | Low input impedance line/bus receiver | Russell J. Houghton, Azzouz Nezar, Wilbur D. Pricer, William R. Tonti | 2002-12-24 |
| 6492211 | Method for novel SOI DRAM BICMOS NPN | Ramachandra Divakaruni, Russell J. Houghton, W. David Pricer, William R. Tonti | 2002-12-10 |
| 6479368 | Method of manufacturing a semiconductor device having a shallow trench isolating region | Mutsuo Morikado, Herbert L. Ho, Jeffrey P. Gambino | 2002-11-12 |
| 6458646 | Asymmetric gates for high density DRAM | Ramachandra Divakaruni, Wayne F. Ellis, Mary E. Weybright | 2002-10-01 |
| 6455886 | Structure and process for compact cell area in a stacked capacitor cell array | Ramachandra Divakaruni, Carl Radens | 2002-09-24 |
| 6452224 | Method for manufacture of improved deep trench eDRAM capacitor and structure produced thereby | Carl Radens | 2002-09-17 |
| 6451648 | Process for buried-strap self-aligned to deep storage trench | Ulrike Gruening, Carl Radens | 2002-09-17 |
| 6444548 | Bitline diffusion with halo for improved array threshold voltage control | Ramachandra Divakaruni, Yujun Li | 2002-09-03 |
| 6444516 | Semi-insulating diffusion barrier for low-resistivity gate conductors | Lawrence A. Clevenger, Rajarao Jammy, Oleg Gluschenkov, Irene McStay, Kwong Hon Wong +1 more | 2002-09-03 |
| 6440793 | Vertical MOSFET | Ramachandra Divakaruni, Heon Lee, Carl Radens, Jai-Hoon Sim | 2002-08-27 |
| 6440801 | Structure for folded architecture pillar memory cell | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Howard L. Kalter +2 more | 2002-08-27 |
| 6440788 | Implant sequence for multi-function semiconductor structure and method | Edward J. Nowak, William R. Tonti | 2002-08-27 |
| 6440872 | Method for hybrid DRAM cell utilizing confined strap isolation | Ramachandra Divakaruni, Carl Radens, Stephan Kudelka | 2002-08-27 |
| 6441422 | Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well | Ramachandra Divakaruni, Carl Radens, Jai-Hoon Sim | 2002-08-27 |
| 6441423 | Trench capacitor with an intrinsically balanced field across the dielectric | Rama Divakaruni | 2002-08-27 |
| 6437401 | Structure and method for improved isolation in trench storage cells | Stephan Kudelka, Andreas Knorr, Stephen Rahn, Helmut Tews, Michael Wise | 2002-08-20 |
| 6436749 | Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion | William R. Tonti, Claude L. Bertin, Jeffrey P. Gambino, Russell J. Houghton, Wilbur D. Pricer | 2002-08-20 |
| 6437388 | Compact trench capacitor memory cell with body contact | Carl Radens, Ulrike Gruening | 2002-08-20 |
| 6432787 | Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact | Ramachandra Divakaruni | 2002-08-13 |
| 6429068 | Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ramachandra Divakaruni, Ulrike Gruening, Larry Nesbit, Carl Radens | 2002-08-06 |
| 6429477 | Shared body and diffusion contact structure and method for fabricating same | Rama Divakaruni, William R. Tonti | 2002-08-06 |
| 6426530 | High performance direct coupled FET memory cell | Claude L. Bertin, John Cronin, Erik L. Hedberg | 2002-07-30 |
| 6426252 | Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap | Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Dan Moy +3 more | 2002-07-30 |