Issued Patents 2002
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6426252 | Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap | Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Dan Moy +3 more | 2002-07-30 |
| 6426526 | Single sided buried strap | Ramachandra Divakaruni, Gary B. Bronner, Carl Radens | 2002-07-30 |
| 6426530 | High performance direct coupled FET memory cell | Claude L. Bertin, John Cronin, Erik L. Hedberg | 2002-07-30 |
| 6424011 | Mixed memory integration with NVRAM, dram and sram cell structures on same substrate | Fariborz Assaderaghi, Louis L. Hsu | 2002-07-23 |
| 6420750 | Structure and method for buried-strap with reduced outdiffusion | Ramachandra Divakaruni | 2002-07-16 |
| 6420749 | Trench field shield in trench isolation | Ramachandra Divakaruni, Jeffrey P. Gambino, Edward W. Kiewra, Carl Radens, William R. Tonti | 2002-07-16 |
| 6414347 | Vertical MOSFET | Ramachandra Divakaruni, Heon Lee, Carl Radens, Jai-Hoon Sim | 2002-07-02 |
| 6410369 | Soi-body selective link method and apparatus | Roy C. Flaker, Louis L. Hsu, Fariborz Assaderaghi | 2002-06-25 |
| 6404000 | Pedestal collar structure for higher charge retention time in trench-type DRAM cells | Rama Divakaruni, Rajarao Jammy, Byeong Y. Kim, Akira Sudo, Dirk Tobben | 2002-06-11 |
| 6399447 | Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor | Lawrence A. Clevenger, Louis L. Hsu, Carl Radens | 2002-06-04 |
| 6396121 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, William R. Tonti | 2002-05-28 |
| 6396120 | Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application | Claude L. Bertin, Toshiharu Furukawa, Erik L. Hedberg, William R. Tonti, Richard Q. Williams | 2002-05-28 |
| 6380027 | Dual tox trench dram structures and process using V-groove | Toshiharu Furukawa, Jeffrey P. Gambino, Edward W. Kiewra, Carl Radens, William R. Tonti +1 more | 2002-04-30 |
| 6376324 | Collar process for reduced deep trench edge bias | Ramachandra Divakaruni, Carl Radens, Ulrike Gruening, Akira Sudo | 2002-04-23 |
| 6373086 | Notched collar isolation for suppression of vertical parasitic MOSFET and the method of preparing the same | Rama Divakaruni, Byeong Y. Kim | 2002-04-16 |
| 6369671 | Voltage controlled transmission line with real-time adaptive control | Claude L. Bertin, Anthony R. Bonaccio, Howard L. Kalter, Thomas M. Maffitt, Edward J. Nowak +1 more | 2002-04-09 |
| 6369419 | Self-aligned near surface strap for high density trench DRAMS | Ramachandra Divakaruni, Jochen Beintner, Ulrike Gruening, Johann Alsmeier, Gary B. Bronner | 2002-04-09 |
| 6362056 | Method of making alternative to dual gate oxide for MOSFETs | William R. Tonti | 2002-03-26 |
| 6355531 | Method for fabricating semiconductor devices with different properties using maskless process | Louis L. Hsu, Carl Radens, William R. Tonti, Li-Kong Wang | 2002-03-12 |
| 6352882 | Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation | Fariborz Assaderaghi, Louis L. Hsu | 2002-03-05 |
| 6352892 | Method of making DRAM trench capacitor | Rajarao Jammy, Carl Radens | 2002-03-05 |
| 6350653 | Embedded DRAM on silicon-on-insulator substrate | James W. Adkisson, Ramachandra Divakaruni, Jeffrey P. Gambino | 2002-02-26 |
| 6348394 | Method and device for array threshold voltage control by trapped charge in trench isolation | Rama Divakaruni, Herbert L. Ho, Giuseppe La Rosa, Yujun Li, Jochen Beintner +1 more | 2002-02-19 |
| 6348374 | Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure | Satish D. Athavale, Gary B. Bronner, Ramachandra Divakaruni, Ulrike Gruening, Carl Radens | 2002-02-19 |
| 6344383 | Structure and method for dual gate oxidation for CMOS technology | Wayne S. Berry, Jeffrey P. Gambino, William R. Tonti | 2002-02-05 |