GB

Gary B. Bronner

IBM: 13 patents #39 of 5,400Top 1%
Infineon Technologies Ag: 1 patents #25 of 113Top 25%
📍 Los Altos, CA: #5 of 415 inventorsTop 2%
🗺 California: #106 of 26,763 inventorsTop 1%
Overall (2002): #896 of 266,432Top 1%
13
Patents 2002

Issued Patents 2002

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
6501117 Static self-refreshing DRAM structure and operating mode Carl Radens, Ramachandra Divakaruni, Jack A. Mandelman 2002-12-31
6495876 DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS Ramachandra Divakaruni, Yoichi Takegawa 2002-12-17
6429474 Storage-capacitor electrode and interconnect Jeffrey P. Gambino, David E. Kotecki, Carl Radens 2002-08-06
6426251 Process for manufacturing a crystal axis-aligned vertical side wall device Ulrike Gruening, Jack A. Mandelman, Carl Radens 2002-07-30
6426526 Single sided buried strap Ramachandra Divakaruni, Jack A. Mandelman, Carl Radens 2002-07-30
6426252 Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap Carl Radens, Tze-Chiang Chen, Bijan Davari, Jack A. Mandelman, Dan Moy +3 more 2002-07-30
6403423 Modified gate processing for optimized definition of array and logic devices on same chip Mary E. Weybright, Richard A. Conti, Ramachandra Divakaruni, Jeffrey P. Gambino, Peter D. Hoh +1 more 2002-06-11
6395594 Method for simultaneously forming a storage-capacitor electrode and interconnect David E. Kotecki, Carl Radens, Jeffrey P. Gambino 2002-05-28
6388294 Integrated circuit using damascene gate structure Carl Radens, Mary E. Weybright 2002-05-14
6369419 Self-aligned near surface strap for high density trench DRAMS Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier 2002-04-09
6348374 Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure Satish D. Athavale, Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman, Carl Radens 2002-02-19
6344389 Self-aligned damascene interconnect Jeffrey P. Gambino, Carl Radens 2002-02-05
6339001 Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist Jeffrey P. Gambino 2002-01-15