Issued Patents 2002
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6486024 | Integrated circuit trench device with a dielectric collar stack, and method of forming thereof | Helmut Tews, Alexander Michaelis, Stephan Kudelka, Uwe Schroeder | 2002-11-26 |
| 6451648 | Process for buried-strap self-aligned to deep storage trench | Jack A. Mandelman, Carl Radens | 2002-09-17 |
| 6437388 | Compact trench capacitor memory cell with body contact | Carl Radens, Jack A. Mandelman | 2002-08-20 |
| 6437381 | Semiconductor memory device with reduced orientation-dependent oxidation in trench structures | Rajarao Jammy, Helmut Tews | 2002-08-20 |
| 6429068 | Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ramachandra Divakaruni, Jack A. Mandelman, Larry Nesbit, Carl Radens | 2002-08-06 |
| 6429092 | Collar formation by selective oxide deposition | Jochen Beintner, Alexander Michaelis, Oswald Spindler, Zvonimir Gabric | 2002-08-06 |
| 6426251 | Process for manufacturing a crystal axis-aligned vertical side wall device | Gary B. Bronner, Jack A. Mandelman, Carl Radens | 2002-07-30 |
| 6399434 | Doped structures containing diffusion barriers | Susan E. Chaloux, Johnathan E. Faltermeier, Rajarao Jammy, Christopher C. Parks, Paul C. Parries +2 more | 2002-06-04 |
| 6399978 | Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region | Carl Radens | 2002-06-04 |
| 6376324 | Collar process for reduced deep trench edge bias | Jack A. Mandelman, Ramachandra Divakaruni, Carl Radens, Akira Sudo | 2002-04-23 |
| 6372567 | Control of oxide thickness in vertical transistor structures | Helmut Tews, Brian Lee | 2002-04-16 |
| 6369419 | Self-aligned near surface strap for high density trench DRAMS | Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Johann Alsmeier, Gary B. Bronner | 2002-04-09 |
| 6362040 | Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates | Helmut Tews, Brian Lee, Raj Jammy, John Faltermeier | 2002-03-26 |
| 6359299 | Apparatus and method for forming controlled deep trench top isolation layers | — | 2002-03-19 |
| 6348374 | Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure | Satish D. Athavale, Gary B. Bronner, Ramachandra Divakaruni, Jack A. Mandelman, Carl Radens | 2002-02-19 |
| 6348388 | Process for fabricating a uniform gate oxide of a vertical transistor | Johnathan E. Faltermeier, Suryanarayan G. Hegde, Rajarao Jammy, Brian Lee, Helmut Tews | 2002-02-19 |
| 6339241 | Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch | Jack A. Mandelman, Ramachandra Divakaruni, Carl Radens | 2002-01-15 |