Issued Patents 2002
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6495445 | Semi-sacrificial diamond for air dielectric formation | Lawrence A. Clevenger | 2002-12-17 |
| 6492662 | T-RAM structure having dual vertical devices and method for fabricating the same | Rajiv V. Joshi | 2002-12-10 |
| 6492227 | Method for fabricating flash memory device using dual damascene process | Li-Kong Wang, Wei Hwang | 2002-12-10 |
| 6469949 | Fuse latch array system for an embedded DRAM having a micro-cell architecture | Li-Kong Wang | 2002-10-22 |
| 6456521 | Hierarchical bitline DRAM architecture system | Rajiv V. Joshi | 2002-09-24 |
| 6452110 | Patterning microelectronic features without using photoresists | Lawrence A. Clevenger, Carl Radens, Li-Kong Wang, Keith Kwong Hon Wong | 2002-09-17 |
| 6452855 | DRAM array interchangeable between single-cell and twin-cell array operation | Rajiv V. Joshi, John A. Fifield, Wayne F. Ellis | 2002-09-17 |
| 6449202 | DRAM direct sensing scheme | Hiroyuki Akatsu, Jeremy K. Stephens, Daniel W. Storaska | 2002-09-10 |
| 6445638 | Folded-bitline dual-port DRAM architecture system | Rajiv V. Joshi, Radens Carl | 2002-09-03 |
| 6445626 | Column redundancy architecture system for an embedded DRAM | Rajiv V. Joshi, Gregory J. Fredeman | 2002-09-03 |
| 6441421 | High dielectric constant materials forming components of DRAM storage cells | Lawrence A. Clevenger, Carl Radens, Joseph F. Shepard, Jr. | 2002-08-27 |
| 6437623 | Data retention registers | Wei Hwang, Stephen V. Kosonocky, Li-Kong Wang | 2002-08-20 |
| 6434076 | Refresh control circuit for low-power SRAM applications | John E. Andersen, Stephen V. Kosonocky, Li-Kong Wang | 2002-08-13 |
| 6433397 | N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same | Lawrence A. Clevenger, Rama Divakaruni, Yujun Li | 2002-08-13 |
| 6426903 | Redundancy arrangement using a focused ion beam | Lawrence A. Clevenger, Li-Kong Wang, Keith Kwong Hon Wong | 2002-07-30 |
| 6426914 | Floating wordline using a dynamic row decoder and bitline VDD precharge | Robert H. Dennard, Toshiaki Kirihata | 2002-07-30 |
| 6424011 | Mixed memory integration with NVRAM, dram and sram cell structures on same substrate | Fariborz Assaderaghi, Jack A. Mandelman | 2002-07-23 |
| 6420216 | Fuse processing using dielectric planarization pillars | Larry Clevenger, Chandrasekhar Narayan, Jeremy K. Stephens, Michael Wise | 2002-07-16 |
| 6411157 | Self-refresh on-chip voltage generator | Li-Kong Wang | 2002-06-25 |
| 6410369 | Soi-body selective link method and apparatus | Roy C. Flaker, Fariborz Assaderaghi, Jack A. Mandelman | 2002-06-25 |
| 6400619 | Micro-cell redundancy scheme for high performance eDRAM | Li-Kong Wang | 2002-06-04 |
| 6399447 | Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor | Lawrence A. Clevenger, Jack A. Mandelman, Carl Radens | 2002-06-04 |
| 6396324 | Clock system for an embedded semiconductor memory unit | Rajiv V. Joshi, Richard Michael Parent, Matthew R. Wordeman | 2002-05-28 |
| 6358791 | Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby | Li-Kong Wang | 2002-03-19 |
| 6356134 | Universal clock generator circuit and adjustment method for providing a plurality of clock frequencies | Lawrence A. Clevenger, Li-Kong Wang, Kevin Guay | 2002-03-12 |