Issued Patents 2002
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6477630 | Hierarchical row activation method for banking control in multi-bank DRAM | Brian L. Ji, Dmitry Netis | 2002-11-05 |
| 6426914 | Floating wordline using a dynamic row decoder and bitline VDD precharge | Robert H. Dennard, Louis L. Hsu | 2002-07-30 |
| 6404264 | Fuse latch having multiplexers with reduced sizes and lower power consumption | Gabriel Daniel | 2002-06-11 |
| 6404689 | Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline | Sang Hoo Dhong, Chorng-Lii Hwang | 2002-06-11 |
| 6400639 | Wordline decoder system and method | Brian L. Ji, Dmitry Netis | 2002-06-04 |
| 6370055 | Semiconductor memory having asymmetric column addressing and twisted read write drive (RWD) line architecture | David R. Hanson, Gerhard Mueller | 2002-04-09 |
| 6338103 | System for high-speed data transfer using a sequence of overlapped global pointer signals for generating corresponding sequence of non-overlapped local pointer signals | — | 2002-01-08 |
| 6335652 | Method and apparatus for the replacement of non-operational metal lines in DRAMS | Gerhard Mueller | 2002-01-01 |