Issued Patents All Time
Showing 101–125 of 244 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10475852 | Resistive switching random access memory with asymmetric source and drain | Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Yu-Wen Liao | 2019-11-12 |
| 10475999 | Metal landing on top electrode of RRAM | Chih-Yang Chang | 2019-11-12 |
| 10388865 | High yield RRAM cell with optimized film scheme | Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao +1 more | 2019-08-20 |
| 10388868 | Resistance variable memory structure and method of forming the same | Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih +2 more | 2019-08-20 |
| 10311952 | Method and apparatus for reading RRAM cell | Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang +4 more | 2019-06-04 |
| 10276790 | Top electrode for device structures in interconnect | Hsia-Wei Chen, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao +2 more | 2019-04-30 |
| 10276489 | Series MIM structures | Kuo-Chi Tu, Chin-Chieh Yang | 2019-04-30 |
| 10276485 | Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Yu-Wen Liao | 2019-04-30 |
| 10262731 | Device and method for forming resistive random access memory cell | Chih-Yang Chang, Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang | 2019-04-16 |
| 10249756 | Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof | Kuo-Chi Tu, Jen-Sheng Yang, Sheng-Hung Shih, Tong-Chern Ong | 2019-04-02 |
| 10199575 | RRAM cell structure with laterally offset BEVA/TEVA | Chih-Yang Chang, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang +2 more | 2019-02-05 |
| 10164169 | Memory device having a single bottom electrode layer | Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Yu-Wen Liao, Kuei-Hung Shen +2 more | 2018-12-25 |
| 10163981 | Metal landing method for RRAM technology | Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu +1 more | 2018-12-25 |
| 10164182 | Switching layer scheme to enhance RRAM performance | Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin | 2018-12-25 |
| 10164185 | RRAM cell with PMOS access transistor | Sheng-Hung Shih, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang +2 more | 2018-12-25 |
| 10158072 | Step height reduction of memory element | Jen-Sheng Yang, Chih-Yang Chang, Chin-Chieh Yang, Kuo-Chi Tu, Sheng-Hung Shih +3 more | 2018-12-18 |
| 10158070 | Logic compatible RRAM structure and process | Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Yu-Wen Liao | 2018-12-18 |
| 10109793 | Bottom electrode for RRAM structure | Jen-Sheng Yang, Yu-Wen Liao | 2018-10-23 |
| 10103330 | Resistance variable memory structure | Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Yu-Wen Liao, Chin-Chieh Yang | 2018-10-16 |
| 10103200 | Resistive switching random access memory with asymmetric source and drain | Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Yu-Wen Liao | 2018-10-16 |
| 10050197 | Resistance variable memory structure | Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Yu-Wen Liao, Chin-Chieh Yang | 2018-08-14 |
| 10038139 | One transistor and one resistive random access memory (RRAM) structure with spacer | Hsia-Wei Chen, Kuo-Chi Tu, Chin-Chieh Yang, Chih-Yang Chang, Yu-Wen Liao | 2018-07-31 |
| 10014469 | Resistive random access memory and manufacturing method thereof | Po-Hao Lee, Chung-Cheng Chou | 2018-07-03 |
| 10008662 | Perpendicular magnetic tunneling junction (MTJ) for improved magnetoresistive random-access memory (MRAM) process | Wen-Chun You, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang +2 more | 2018-06-26 |
| 9966139 | Resistive random access memory device | Chung-Cheng Chou, Yu-Der Chih | 2018-05-08 |