Issued Patents All Time
Showing 51–75 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10340181 | Interconnect structure including air gap | Wei-Chen Chu, Hsin-Ping Chen, Chih Wei Lu, Chung-Ju Lee | 2019-07-02 |
| 10325993 | Gate all around device and fabrication thereof | Yung-Chih Wang, Yu-Chieh Liao, Hsin-Ping Chen | 2019-06-18 |
| 10290580 | Hybrid copper structure for advance interconnect usage | Hsiang-Wei Liu, Cheng-Chi Chuang, Tien-Lu Lin | 2019-05-14 |
| 10276498 | Interconnect structure with air-gaps | Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin | 2019-04-30 |
| 10269915 | Vertical MOS transistor and fabricating method thereof | Yung-Chih Wang, Shin-Yi Yang, Chih Wei Lu, Hsin-Ping Chen, Shau-Lin Shue | 2019-04-23 |
| 10177242 | Semiconductor arrangement and formation thereof | Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu | 2019-01-08 |
| 10163690 | 2-D interconnections for integrated circuits | Chia-Tien Wu, Hsiang-Wei Liu, Wei-Chen Chu | 2018-12-25 |
| 10103102 | Structure and formation method of semiconductor device structure | Jian-Hua Chen, Cheng-Chi Chuang, Chia-Tien Wu, Tien-Lu Lin, Tien-I Bao | 2018-10-16 |
| 10074607 | Semiconductor device structure with graphene layer | Tien-I Bao, Tien-Lu Lin, Wei-Chen Chu | 2018-09-11 |
| 10049941 | Semiconductor isolation structure with air gaps in deep trenches | Hong-Seng Shue, Wei-Ding Wu, Ming-Tai Chung, Shao-Chi Yu | 2018-08-14 |
| 10026647 | Multi-metal fill with self-align patterning | Wei-Chen Chu, Cheng-Chi Chuang, Chia-Tien Wu | 2018-07-17 |
| 10000373 | Nano-electromechanical system (NEMS) device structure and method for forming the same | Hsin-Ping Chen, Carlos H. Diaz, Ken-Ichi Goto, Shau-Lin Shue | 2018-06-19 |
| 10002826 | Semiconductor device structure with conductive pillar and conductive line and method for forming the same | Yu-Chieh Liao, Tien-Lu Lin, Tien-I Bao | 2018-06-19 |
| 9875967 | Interconnect structure with air-gaps | Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin | 2018-01-23 |
| 9865539 | Structure and formation method of semiconductor device structure | Jian-Hua Chen, Cheng-Chi Chuang, Chia-Tien Wu, Tien-Lu Lin, Tien-I Bao | 2018-01-09 |
| 9837354 | Hybrid copper structure for advance interconnect usage | Hsiang-Wei Liu, Cheng-Chi Chuang, Tien-Lu Lin | 2017-12-05 |
| 9805970 | Method for forming deep trench spacing isolation for CMOS image sensors | Jung-I Lin, Ta-Chun Lin, Tien-Lu Lin, Chen-Jong Wang | 2017-10-31 |
| 9735232 | Method for manufacturing a semiconductor structure having a trench with high aspect ratio | Jheng-Sheng YOU, Chi-Fu Lin, Tien-Lu Lin | 2017-08-15 |
| 9716035 | Combination interconnect structure and methods of forming same | Yung-Chih Wang, Cheng-Chi Chuang, Chia-Tien Wu, Tien-Lu Lin | 2017-07-25 |
| 9698242 | Semiconductor arrangement and formation thereof | Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu | 2017-07-04 |
| 9633897 | Air-gap forming techniques for interconnect structures | Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin | 2017-04-25 |
| 9614031 | Methods for forming a high-voltage super junction by trench and epitaxial doping | Shou-Wei Lee, Shao-Chi Yu, Hong-Seng Shue, Kun-Ming Huang, Po-Tao Chu | 2017-04-04 |
| 9595471 | Conductive element structure and method | Hsiang-Wei Liu, Chia-Tien Wu, Hsiang-Huan Lee, Tien-Lu Lin | 2017-03-14 |
| 9583434 | Metal line structure and method | Hsiang-Lun Kao, Hsiang-Wei Liu, Jian-Hua Chen, Yu-Chieh Liao, Yung-Chih Wang +1 more | 2017-02-28 |
| 9576896 | Semiconductor arrangement and formation thereof | Yu-Chieh Liao, Cheng-Chi Chuang, Tien-Lu Lin, Yung-Hsu Wu | 2017-02-21 |