MC

Min Cao

TSMC: 54 patents #599 of 12,232Top 5%
AT Agilent Technologies: 14 patents #94 of 3,411Top 3%
CS Cadence Design Systems: 9 patents #141 of 2,263Top 7%
HP HP: 5 patents #933 of 7,018Top 15%
Bank of America: 4 patents #945 of 5,361Top 20%
PS Pericom Semiconductor: 3 patents #22 of 67Top 35%
KC Kingfa Sci. & Tech. Co.: 2 patents #22 of 88Top 25%
OC Ocean University Of China: 1 patents #46 of 243Top 20%
CC China Railway Tunnel Group Co.: 1 patents #6 of 55Top 15%
CI Cisco: 1 patents #7,901 of 13,007Top 65%
HE Hewlett Packard Enterprise: 1 patents #2,081 of 4,473Top 50%
AN Aruba Networks: 1 patents #145 of 255Top 60%
NU Nanjing University: 1 patents #249 of 887Top 30%
NA Nec Laboratories America: 1 patents #215 of 412Top 55%
📍 Hsinchu, CA: #26 of 400 inventorsTop 7%
Overall (All Time): #12,561 of 4,157,543Top 1%
107
Patents All Time

Issued Patents All Time

Showing 76–100 of 107 patents

Patent #TitleCo-InventorsDate
7943961 Strain bars in stressed layers of MOS devices Yen-Sen Wang, Chung-Te Lin, Sheng-Jier Yang 2011-05-17
7944023 Strained Si formed by anneal 2011-05-17
7825477 Semiconductor device with localized stressor Ru-Shang Hsiao, Chung-Te Lin, Ta-Ming Kuan, Cheng-Tung Hsu 2010-11-02
7772062 MOSFET having a channel mechanically stressed by an epitaxially grown, high k strain layer 2010-08-10
7657856 Method and system for parallel processing of IC design layouts Mathew Koshy, Roland Ruehl, Li Ma, Eitan Cadouri, Tianhao Zhang 2010-02-02
7567543 Method and apparatus for cross layer resource allocation for wireless backhaul networks Xiaodong Wang, Seung Jun Kim, Mohammad Madihian 2009-07-28
7305651 Mask CD correction based on global pattern density 2007-12-04
7202145 Strained Si formed by anneal 2007-04-10
7038242 Amorphous semiconductor open base phototransistor array Paul J. Vande Voorde, Frederick Perner, Dietrich W. Vook 2006-05-02
7015129 Bond pad scheme for Cu process Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Huan Chi Tseng, Yu-Hua Lee +1 more 2006-03-21
6844626 Bond pad scheme for Cu process Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Huan Chi Tseng, Yu-Hua Lee +1 more 2005-01-18
6794707 Variable capacitor using MOS gated diode with multiple segments to limit DC current 2004-09-21
6765280 Local oxidation of a sidewall sealed shallow trench for providing isolation between devices of a substrate Paul J. Vande Voorde, Wayne M. Greene, Malahat Tavassoli 2004-07-20
6759724 Isolation of alpha silicon diode sensors through ion implantation Jeremy Alfred Theil, Gary W. Ray, Dietrich W. Vook 2004-07-06
6674116 Variable capacitor using MOS gated diode with multiple segments to limit DC current 2004-01-06
6586812 Isolation of alpha silicon diode sensors through ion implantation Jeremy Alfred Theil, Gary W. Ray, Dietrich W. Vook 2003-07-01
6545711 Photo diode pixel sensor array having a guard ring Frederick Perner, Charles M. C. Tan, Jeremy Alfred Theil 2003-04-08
6541814 MOS variable capacitor with controlled dC/dV and voltage drop across W of gate Hide Hattori 2003-04-01
6396118 Conductive mesh bias connection for an array of elevated active pixel sensors Jeremy Alfred Theil, Jane M. Lin, Gary W. Ray, Shawming Ma, Xin Sun 2002-05-28
6387736 Method and structure for bonding layers in a semiconductor device Jeremy Alfred Theil, Gary W. Ray, Dietrich W. Vook 2002-05-14
6384460 Self-aligned metal electrode structure for elevated sensors Jeremy Alfred Theil 2002-05-07
6376275 Fabrication of self-aligned metal electrode structure for elevated sensors Jeremy Alfred Theil 2002-04-23
6315384 Thermal inkjet printhead and high-efficiency polycrystalline silicon resistor system for use therein Ravi Ramaswami, Victor Joseph, Theodore I. Kamins, John Whitlock, Anil Prem 2001-11-13
6267471 High-efficiency polycrystalline silicon resistor system for use in a thermal inkjet printhead Ravi Ramaswami, Victor Joseph 2001-07-31
6265325 Method for fabricating dual gate dielectric layers Dietrich W. Vook 2001-07-24