Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8429588 | Method and mechanism for extraction and recognition of polygons in an IC design | Anwar Adkhamovich Irmatov, Alexander Belousov, Andrei Gratchev, Alexander Ryjov, Laurent Thenie | 2013-04-23 |
| 7913206 | Method and mechanism for performing partitioning of DRC operations | — | 2011-03-22 |
| 7908579 | Method and mechanism for extraction and recognition of polygons in an IC design | Anwar Adkhamovich Irmatov, Alexander Belousov, Andrei Gratchev, Alexander Ryjov, Laurent Thenie | 2011-03-15 |
| 7904852 | Method and system for implementing parallel processing of electronic design automation tools | Krzysztof A. Kozminski, Haifang Liao, Kenneth Mednick, Roland Ruehl, Mark A. Snowden | 2011-03-08 |
| 7657856 | Method and system for parallel processing of IC design layouts | Mathew Koshy, Roland Ruehl, Min Cao, Li Ma, Tianhao Zhang | 2010-02-02 |
| 7617465 | Method and mechanism for performing latch-up check on an IC design | — | 2009-11-10 |
| 7555736 | Method and system for using pattern matching to process an integrated circuit design | — | 2009-06-30 |
| 7508071 | Adjusting die placement on a semiconductor wafer to increase yield | — | 2009-03-24 |
| 7440869 | Mapping yield information of semiconductor dice | — | 2008-10-21 |
| 7418682 | Method and mechanism for performing DRC processing with reduced passes through an IC design | — | 2008-08-26 |
| 7334205 | Optimization of die placement on wafers | — | 2008-02-19 |
| 7220605 | Selecting dice to test using a yield map | — | 2007-05-22 |
| 7190183 | Selecting die placement on a semiconductor wafer to reduce test time | — | 2007-03-13 |
| 7169638 | Adjusting die placement on a semiconductor wafer to increase yield | — | 2007-01-30 |
| 7039543 | Transforming yield information of a semiconductor fabrication process | — | 2006-05-02 |
| 6826738 | Optimization of die placement on wafers | — | 2004-11-30 |