KM

Kenneth Mednick

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
📍 San Jose, CA: #17,604 of 32,062 inventorsTop 55%
🗺 California: #185,134 of 386,348 inventorsTop 50%
Overall (All Time): #2,103,999 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
7904852 Method and system for implementing parallel processing of electronic design automation tools Eitan Cadouri, Krzysztof A. Kozminski, Haifang Liao, Roland Ruehl, Mark A. Snowden 2011-03-08
7243321 IC layout physical verification method Xiaojun Wang 2007-07-10