Issued Patents All Time
Showing 76–100 of 125 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9711372 | Double patterning method | Chia-Ying Lee | 2017-07-18 |
| 9627250 | Method and apparatus for back end of line semiconductor device processing | Chung-Wen Wu, Chih-Yuan Ting | 2017-04-18 |
| 9613903 | Fine line space resolution lithography structure for integrated circuit features using double patterning technology | Chia-Ying Lee | 2017-04-04 |
| 9601348 | Interconnect structure and method of forming same | Ming-Hui Chu, Chih-Yuan Ting | 2017-03-21 |
| 9601344 | Method of forming pattern for semiconductor device | Chia-Ying Lee, Chih-Yuan Ting, Ming-Hsing Tsai, Syun-Ming Jang | 2017-03-21 |
| 9570341 | Semiconductor device having air gap structures and method of fabricating thereof | Chih-Yuan Ting | 2017-02-14 |
| 9564327 | Method for forming line end space structure using trimmed photo resist | Chia-Ying Lee, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh +1 more | 2017-02-07 |
| 9524902 | Method of forming integrated circuit with conductive line having line-ends | Pei-Wen Huang, Chih-Yuan Ting | 2016-12-20 |
| 9502287 | Method of preventing pattern collapse | Chih-Yuan Ting, Chung-Wen Wu, Jeng-Shiou Chen, Jang-Shiang Tsai | 2016-11-22 |
| 9502261 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2016-11-22 |
| 9496224 | Semiconductor device having air gap structures and method of fabricating thereof | Chih-Yuan Ting | 2016-11-15 |
| 9472448 | Contact plug without seam hole and methods of forming the same | Chih-Yuan Ting | 2016-10-18 |
| 9401329 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Minghsing Tsai | 2016-07-26 |
| 9397047 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Ming-Hsing Tsai | 2016-07-19 |
| 9240346 | Double patterning method | Chia-Ying Lee | 2016-01-19 |
| 9204538 | Method of fine line space resolution lithography for integrated circuit features using double patterning technology | Chia-Ying Lee | 2015-12-01 |
| 9153478 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Shih-Ming Chang, Ken-Hsien Hsieh, Ming-Feng Shieh, Chih-Ming Lai +6 more | 2015-10-06 |
| 9153479 | Method of preventing a pattern collapse | Chih-Yuan Ting, Chung-Wen Wu, Jeng-Shiou Chen, Jang-Shiang Tsai | 2015-10-06 |
| 9142450 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Minghsing Tsai | 2015-09-22 |
| 9123656 | Organosilicate polymer mandrel for self-aligned double patterning process | Wen-Kuo Hsieh, Ming-Chung Liang | 2015-09-01 |
| 9040433 | Photo resist trimmed line end space | Chia-Ying Lee, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh +1 more | 2015-05-26 |
| 8987142 | Multi-patterning method and device formed by the method | Chia-Ying Lee | 2015-03-24 |
| 8962484 | Method of forming pattern for semiconductor device | Chia-Ying Lee, Chih-Yuan Ting, Minghsing Tsai, Syun-Ming Jang | 2015-02-24 |
| 8962432 | Semiconductor device with self aligned end-to-end conductive line structure and method for forming the same | Chia-Ying Lee | 2015-02-24 |
| 8865600 | Patterned line end space | Chia-Ying Lee | 2014-10-21 |